Semiconductor package and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-12543605-B2
Application number	US-202318227646-A
Country	US
Kind code	B2
Filing date	Jul 28, 2023
Priority date	Dec 23, 2022
Publication date	Feb 3, 2026
Grant date	Feb 3, 2026

Abstract

The present disclosure provides semiconductor packages and methods of fabricating the same. In some embodiments, a semiconductor package includes a substrate including first and second regions, a first pad on the first region, a second pad on the second region, a first dielectric layer on the first region and including a first opening exposing the first pad, a second dielectric layer on the second region and including a second opening exposing the second pad, a first bump structure on the first pad and in the first opening, and a second bump structure on the second pad and in the second opening. A thickness of the first dielectric layer is greater than a thickness of the second dielectric layer. A distance between the substrate and an uppermost end of the first bump structure is longer than a distance between the substrate and an uppermost end of the second bump structure.

First claim

What is claimed is:

1 . A semiconductor package, comprising:
a substrate comprising a first region and a second region spaced apart from the first region; a first pad on the substrate of the first region; a second pad on the substrate of the second region; a first dielectric layer disposed on the substrate on the first region, the first dielectric layer comprising a first opening that exposes the first pad; a second dielectric layer disposed on the substrate on the second region, the second dielectric layer comprising a second opening that exposes the second pad; a first bump structure disposed on the first pad and in the first opening of the first dielectric layer; and a second bump structure disposed on the second pad and in the second opening of the second dielectric layer, wherein a first thickness of the first dielectric layer is greater than a second thickness of the second dielectric layer, and wherein a first distance between the substrate and an uppermost end of the first bump structure is longer than a second distance between the substrate and an uppermost end of the second bump structure.

2 . The semiconductor package of claim 1 , wherein:
the first bump structure fills the first opening, and the second bump structure fills the second opening.

3 . The semiconductor package of claim 2 , wherein a first width of the first opening is less than a second width of the second opening.

4 . The semiconductor package of claim 3 , wherein the second width of the second opening is about 1.1 times to about 1.5 times the first width of the first opening.

5 . The semiconductor package of claim 2 , wherein:
at least a first portion of the first bump structure extends onto the first dielectric layer, and at least a second portion of the second bump structure extends onto the second dielectric layer.

6 . The semiconductor package of claim 1 , wherein a difference between the first thickness of the first dielectric layer and the second thickness of the second dielectric layer is about 20% to about 80% of the first thickness of the first dielectric layer.

7 . The semiconductor package of claim 1 , wherein a difference between the first distance and the second distance is about 2% to about 10% of the first distance.

8 . The semiconductor package of claim 1 , wherein:
the first bump structure comprises:
a first conductive post penetrating the first dielectric layer and coupled to the first pad; and
a first solder bump on the first conductive post, and
the second bump structure comprises:
a second conductive post penetrating the second dielectric layer and coupled to the second pad; and
a second solder bump on the second conductive post.

9 . The semiconductor package of claim 1 , wherein the substrate has a shape in which a first recess level of the first region is deeper than a second recess level of the second region.

10 . The semiconductor package of claim 1 , further comprising:
a semiconductor chip on a second surface of the substrate, the second surface being opposite to a first surface on which the first pad and the second pad are disposed; and a molding layer disposed on the second surface of the substrate, the molding layer burying the semiconductor chip.

11 . The semiconductor package of claim 1 , wherein
the substrate comprises a semiconductor substrate, the semiconductor substrate comprises:
an integrated circuit on a surface of the semiconductor substrate; and
a plurality of through electrodes that penetrate the semiconductor substrate, and
the first pad and the second pad are electrically coupled to at least one of the integrated circuit and the plurality of through electrodes.

12 . A semiconductor package, comprising:
a substrate comprising a central region and a peripheral region that surrounds the central region; a first pad on the central region on a bottom surface of the substrate; a second pad on the peripheral region on the bottom surface of the substrate; a dielectric layer on the bottom surface of the substrate and disposed on the first pad and the second pad, the dielectric layer comprising a first opening that exposes at least a portion of a bottom surface of the first pad and a second opening that exposes at least a portion of a bottom surface of the second pad; a first bump structure on the dielectric layer on the central region and coupled through the first opening to the first pad; a second bump structure on the dielectric layer on the peripheral region and coupled through the second opening to the second pad; a semiconductor chip on a top surface of the substrate; and a molding layer covering the top surface of the substrate and burying the semiconductor chip, wherein the substrate has a concave shape, wherein a first recess level of the central region is deeper than a second recess level of the peripheral region, wherein a first thickness of the dielectric layer on the first pad is greater than a second thickness of the dielectric layer on the second pad, and wherein a first width of the first opening is less than a second width of the second opening.

13 . The semiconductor package of claim 12 , wherein a first height of the first bump structure is greater than a second height of the second bump structure.

14 . The semiconductor package of claim 13 , wherein a difference between the first height and the second height is about 2% to about 10% of the first height.

15 . The semiconductor package of claim 12 , wherein:
the first bump structure fills the first opening, and the second bump structure fills the second opening.

16 . The semiconductor package of claim 15 , wherein:
at least a first portion of the first bump structure extends onto the dielectric layer, and at least a second portion of the second bump structure extends onto the dielectric layer.

17 . The semiconductor package of claim 12 , wherein the second width of the second opening is about 1.1 times to about 1.5 times the first width of the first opening.

18 . The semiconductor package of claim 12 , wherein a difference between the first thickness and the second thickness is about 20% to about 80% of the first thickness.

19 . The semiconductor package of claim 12 , wherein:
the first bump structure comprises:
a first conductive post penetrating the dielectric layer and coupled to the first pad; and
a first solder bump on the first conductive post, and
the second bump structure comprises:
a second conductive post penetrating the dielectric layer and coupled to the second pad; and
a second solder bump on the second conductive post.

20 . A semiconductor package, comprising:
a substrate comprising a first region and a second region spaced apart from the first region; a first pad on the substrate of the first region; a second pad on the substrate of the second region; a dielectric layer on the substrate and covering at least a first portion of the first pad and at least a second portion of the second pad, the dielectric layer comprising a first opening that exposes at least a third portion of a top surface of the first pad and a second opening that exposes at least a fourth portion of a top surface of the second pad; a first bump structure on the dielectric layer and coupled through the first opening to the first pad; and a second bump structure on the dielectric layer and coupled through the second opening to the second pad, wherein a difference between a first thickness of the dielectric layer on the first re

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Sungwoo
• Kim Yongjae
• Kim Heonwoo
• Ryu Seung-Kwan

Classifications

• H01L2924/37001

  Electricity · mapped topic

• H01L2225/06544

  Electricity · mapped topic

• H01L2225/06517

  Electricity · mapped topic

• H01L2224/1703

  Electricity · mapped topic

• H01L2224/16225

  Electricity · mapped topic