Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-12543345-B2
Application number	US-202318136975-A
Country	US
Kind code	B2
Filing date	Apr 20, 2023
Priority date	Sep 2, 2022
Publication date	Feb 3, 2026
Grant date	Feb 3, 2026

Abstract

A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns spaced apart from each other, a source/drain pattern connected to the plurality of semiconductor patterns, a gate electrode including, an inner electrode between a first semiconductor pattern of the plurality of semiconductor patterns and a second semiconductor pattern of the plurality of semiconductor patterns, the first semiconductor pattern and the second semiconductor pattern being adjacent to each other, and an outer electrode on an uppermost semiconductor pattern of the plurality of semiconductor patterns.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate comprising an active pattern; a channel pattern on the active pattern, the channel pattern comprising a plurality of semiconductor patterns spaced apart from each other; a source/drain pattern connected to the plurality of semiconductor patterns; a gate electrode comprising:
an inner electrode between a first semiconductor pattern of the plurality of semiconductor patterns and a second semiconductor pattern of the plurality of semiconductor patterns, the first semiconductor pattern and the second semiconductor pattern being adjacent to each other, and
an outer electrode on an uppermost semiconductor pattern of the plurality of semiconductor patterns; and
a gate insulating layer comprising:
an inner gate insulating layer adjacent to the inner electrode; and
an outer gate insulating layer adjacent to the outer electrode,
wherein the inner gate insulating layer comprises:
a first portion between the inner electrode and the source/drain pattern; and
a second portion between the inner electrode and the first semiconductor pattern, and
wherein a first thickness of the first portion is about 1.3 times to about 3.0 times a second thickness of the second portion.

2 . The semiconductor device of claim 1 , wherein the first thickness ranges from about 8.0 Å to about 12.0 Å.

3 . The semiconductor device of claim 1 , wherein the second thickness ranges from about 11.0 Å to about 16.0 Å.

4 . The semiconductor device of claim 1 , wherein the gate insulating layer comprises a silicon oxide layer or a silicon oxynitride layer.

5 . The semiconductor device of claim 1 , further comprising a high-k dielectric layer between the inner electrode and the inner gate insulating layer,
wherein the high-k dielectric layer comprises a uniform thickness; and wherein the high-k dielectric layer encloses the inner electrode.

6 . The semiconductor device of claim 5 , wherein the first portion of the inner gate insulating layer comprises a first side surface contacting the source/drain pattern,
wherein the high-k dielectric layer comprises a second side surface contacting the first portion, wherein the inner electrode comprises a third side surface contacting the high-k dielectric layer, and where each of the first side surface, the second side surface and the third side surface comprises a concave portion.

7 . The semiconductor device of claim 6 , wherein a distance between the first side surface and the second side surface is substantially uniform.

8 . The semiconductor device of claim 6 , wherein each of the first side surface, the second side surface, and the third side surface comprises a wavy profile.

9 . The semiconductor device of claim 1 , wherein the outer gate insulating layer comprises:
a third portion between the outer electrode and a gate spacer; and a fourth portion between the outer electrode and the uppermost semiconductor pattern of the plurality of semiconductor patterns, and wherein a third thickness of the third portion is substantially equal to a fourth thickness of the fourth portion.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Baek Sangwon
• Park Beomjin
• Kang Myung Gil
• Kim Dongwon
• Yoo Hyumin
• Cho Namkyu

Classifications

• H10D30/6736

  characterised by the shape of gate insulators · CPC title

• H10D84/85 Primary

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D30/43 Primary

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title