Semiconductor device

Patent metadata

Field	Value
Publication number	US-11227914-B2
Application number	US-202016776677-A
Country	US
Kind code	B2
Filing date	Jan 30, 2020
Priority date	Jul 29, 2019
Publication date	Jan 18, 2022
Grant date	Jan 18, 2022

Abstract

A semiconductor device includes a substrate having a first region and a second region, first and second nanowires disposed sequentially on the substrate in the first region, and extending respectively in a first direction, third and fourth nanowires disposed sequentially on the substrate in the second region, and extending respectively in the first direction, a first inner spacer between the first nanowire and the second nanowire, and including hydrogen of a first hydrogen mole fraction, and a second inner spacer between the third nanowire and the fourth nanowire, and including hydrogen of a second hydrogen mole fraction that is greater than the first hydrogen mole fraction.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate having a first region and a second region;
first and second nanowires disposed sequentially on the substrate in the first region, and extending respectively in a first direction;
third and fourth nanowires disposed sequentially on the substrate in the second region, and extending respectively in the first direction;
a first inner spacer between the first nanowire and the second nanowire, and including hydrogen of a first hydrogen mole fraction; and
a second inner spacer between the third nanowire and the fourth nanowire, and including hydrogen of a second hydrogen mole fraction that is greater than the first hydrogen mole fraction.

2. The semiconductor device of claim 1 , wherein:
the first inner spacer includes oxygen of a first oxygen mole fraction, and
the second inner spacer includes oxygen of a second oxygen mole fraction that is greater than the first oxygen mole fraction.

3. The semiconductor device of claim 1 , wherein:
the first inner spacer and the second inner spacer are disposed at a same level, and
a first thickness in the first direction of the first inner spacer is greater than a second thickness in the first direction of the second inner spacer.

4. The semiconductor device of claim 3 , wherein:
the first thickness of the first inner spacer is 3 nm to 5 nm, and
the second thickness of the second inner spacer is 2 nm to 4 nm.

5. The semiconductor device of claim 1 , wherein the first inner spacer and the second inner spacer include different materials from each other.

6. The semiconductor device of claim 5 , wherein the first inner spacer includes SiN and the second inner spacer includes SiON.

7. The semiconductor device of claim 1 , further comprising:
a third inner spacer on the first inner spacer between the first nanowire and the second nanowire, and
a fourth inner spacer on the second inner spacer between the third nanowire and the fourth nanowire.

8. The semiconductor device of claim 7 , wherein the first and second inner spacers include different materials from those of the third and fourth inner spacers.

9. The semiconductor device of claim 8 , wherein:
each of the first and second inner spacers includes SiON, and
each of the third and fourth inner spacers includes SiN.

10. The semiconductor device of claim 1 , further comprising:
a first gate electrode surrounding the first and second nanowires and extending in a second direction different from the first direction, and
a second gate electrode surrounding the third and fourth nanowires and extending in the second direction.

11. The semiconductor device of claim 1 , wherein a threshold voltage of the first region is different from a threshold voltage of the second region.

12. A semiconductor device, comprising:
a substrate having a first region and a second region;
first and second nanowires disposed sequentially on the substrate in the first region and extending respectively in a first direction;
third and fourth nanowires disposed sequentially on the substrate in the second region and extending respectively in the first direction;
a first gate electrode surrounding the first and second nanowires and extending in a second direction different from the first direction;
a second gate electrode surrounding the third and fourth nanowires and extending in the second direction;
a first inner spacer on at least one side of the first gate electrode between the first nanowire and the second nanowire, and including oxygen of a first oxygen mole fraction; and
a second inner spacer on at least one side of the second gate electrode between the third nanowire and the fourth nanowire, and including oxygen of a second oxygen mole fraction that is greater than the first oxygen mole fraction.

13. The semiconductor device of claim 12 , wherein:
the first inner spacer includes hydrogen of a first hydrogen mole fraction, and
the second inner spacer includes hydrogen of a second hydrogen mole fraction that is greater than the first hydrogen mole fraction.

14. The semiconductor device of claim 12 , wherein:
the first inner spacer and the second inner spacer are disposed at a same level, and
a first thickness in the first direction of the first inner spacer is greater than a second thickness in the first direction of the second inner spacer.

15. The semiconductor device of claim 12 , wherein the first inner spacer and the second inner spacer include a same material.

16. The semiconductor device of claim 12 , further comprising:
a third inner spacer on the first inner spacer between the first nanowire and the second nanowire, and
a fourth inner spacer on the second inner spacer between the third nanowire and the fourth nanowire.

17. A semiconductor device, comprising:
a substrate having a first region and a second region;
first to third nanowires disposed sequentially on the substrate in the first region and extending respectively in a first direction;
fourth to sixth nanowires disposed sequentially on the substrate in the second region and extending respectively in the first direction;
a first gate electrode surrounding the first to third nanowires and extending in a second direction different from the first direction;
a second gate electrode surrounding the fourth to sixth nanowires and extending in the second direction;
a first source/drain region on at least one side of the first to third nanowires;
a second source/drain region on at least one side of the fourth to sixth nanowires;
a first inner spacer on at least one side of the first gate electrode between the first nanowire and the second nanowire, and including oxygen of a first oxygen mole fraction and hydrogen of a first hydrogen mole fraction;
a second inner spacer on at least one side of the second gate electrode between the fourth nanowire and the fifth nanowire, and including oxygen of a second oxygen mole fraction that is greater than the first oxygen mole fraction, and hydrogen of a second hydrogen mole fraction that is greater than the first hydrogen mole fraction;
a first source/drain contact connected with the first source/drain region; and
a second source/drain contact connected with the second source/drain region.

18. The semiconductor device of claim 17 , further comprising:
a third inner spacer on the first inner spacer between the first nanowire and the second nanowire, and
a fourth inner spacer on the second inner spacer between the fourth nanowire and the fifth nanowire.

19. The semiconductor device of claim 17 , wherein the first inner spacer includes SiN, and the second inner spacer includes SiON.

20. The semiconductor device of claim 17 , wherein each of the first inner spacer and the second inner spacer includes SiON.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Shin Woo Cheol
• Kim Sun Wook
• Song Seung Min
• Lee Nam Hyun

Classifications

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D84/0184

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/853 Primary

  comprising FinFETs · CPC title

• H10D62/292

  Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512) · CPC title