Systems and methods for asynchronous data flow in digital radios

Patent metadata

Field	Value
Publication number	US-12542572-B2
Application number	US-202418617336-A
Country	US
Kind code	B2
Filing date	Mar 26, 2024
Priority date	Mar 27, 2023
Publication date	Feb 3, 2026
Grant date	Feb 3, 2026

Abstract

Systems and methods for asynchronous data flow in digital radios are provided. In one aspect, a demodulator circuit includes a receiver circuit configured to receive: a plurality of samples of a radio frequency signal received from a tuner, a clock, and a target size value, the receiver circuit further configured to output the samples at a first rate based on the target size value. The demodulator circuit also includes a sample rate converter configured to receive the samples from the receiver circuit and output the samples at a second rate based on a rate offset value, and a buffer configured to receive the samples from the sample rate converter and output the samples. The demodulator circuit further includes a digital demodulator configured to receive the samples from the buffer and demodulate the samples, and a control loop configured to generate the target size value.

First claim

What is claimed is:

1 . A demodulator circuit comprising:
a receiver circuit configured to receive a clock, a plurality of samples of a radio frequency signal received from a tuner, and a target size value, the receiver circuit further configured to output the samples at a first rate based on the target size value; a sample rate converter configured to receive the samples from the receiver circuit and a rate offset value, and to output the samples at a second rate based on the rate offset value; a buffer configured to receive the samples from the sample rate converter; a digital demodulator configured to receive the samples from the buffer and demodulate the samples; and a control loop configured to generate the target size value to prevent the buffer from underflowing and from overflowing.

2 . The demodulator circuit of claim 1 wherein the digital demodulator is further configured to synchronize with the tuner and generate an ideal request size value based on the synchronizing with the tuner, the control loop further configured to generate the target size value based at least in part on the ideal request size value.

3 . The demodulator circuit of claim 2 wherein the control loop includes:
a first combiner configured to output a difference value between half of a size of the buffer and a current volume of samples in the buffer;
a loop filter configured to receive the difference value from the first combiner and generate a delta value; and
a second combiner configured to receive the delta value from the loop filter and the ideal request size value from the digital demodulator, the second combiner further configured to generate the target size value based on the delta value and the ideal request size value.

4 . The demodulator circuit of claim 1 wherein the receiver circuit includes an inter integrated circuit sound receiver.

5 . The demodulator circuit of claim 1 further comprising a clock generator configured to generate a demodulator clock, wherein the demodulator clock is asynchronous with a tuner clock of the tuner.

6 . The demodulator circuit of claim 1 wherein the sample rate converter, the buffer, the digital demodulator, and the control loop are implemented by a software function.

7 . The demodulator circuit of claim 6 wherein the receiver circuit includes an internal buffer and the receiver circuit is configured to execute the software function in response to a current volume of samples in the internal buffer being equal to the target size.

8 . A digital radio system comprising:
a tuner circuit configured to receive a passband radio frequency signal and convert the passband radio frequency signal into a baseband signal; and a demodulator circuit including: a receiver circuit configured to receive a clock, a plurality of samples of a radio frequency signal received from the tuner circuit, and a target size value, the receiver circuit further configured to output the samples at a first rate based on the target size value; a sample rate converter configured to receive the samples from the receiver circuit and a rate offset value, and to output the samples at a second rate based on the rate offset value; a buffer configured to receive the samples from the sample rate converter; a digital demodulator configured to receive the samples from the buffer and demodulate the samples; and a control loop configured to generate the target size value to prevent the buffer from underflowing and from overflowing.

9 . The digital radio system of claim 8 wherein the digital demodulator is further configured to synchronize with the tuner circuit and generate an ideal request size value based on the synchronizing with the tuner circuit, the control loop further configured to generate the target size value based at least in part on the ideal request size value.

10 . The digital radio system of claim 9 wherein the control loop includes:
a first combiner configured to output a difference value between half of a size of the buffer and a current volume of samples in the buffer;
a loop filter configured to receive the difference value from the first combiner and generate a delta value; and
a second combiner configured to receive the delta value from the loop filter and the ideal request size value from the digital demodulator, the second combiner further configured to generate the target size value based on the delta value and the ideal request size value.

11 . The digital radio system of claim 8 wherein the receiver circuit includes an inter integrated circuit sound receiver.

12 . The digital radio system of claim 8 wherein the demodulator further includes a clock generator configured to generate a demodulator clock, wherein the demodulator clock is asynchronous with a tuner clock of the tuner circuit.

13 . The digital radio system of claim 8 wherein the sample rate converter, the buffer, the digital demodulator, and the control loop are implemented by a software function.

14 . The digital radio system of claim 13 wherein the receiver circuit includes an internal buffer and the receiver circuit is configured to execute the software function in response to a current volume of samples in the internal buffer being equal to the target size.

15 . A method of demodulating a radio frequency signal comprising:
receiving, at a receiver circuit, a plurality of samples of a radio frequency signal received from a tuner, a clock, and a target size value; outputting, from the receiver circuit, the samples at a first rate based on the target size value; receiving, at a sample rate converter, the samples from the receiver circuit and a rate offset value; outputting, from the sample rate converter, the samples at a second rate based on the rate offset value; receiving, at a buffer, the samples from the sample rate converter; outputting the samples from the buffer; demodulating, at a digital demodulator, the samples received from the buffer; and generating, at a control loop, the target size value to prevent the buffer from underflowing and from overflowing.

16 . The method of claim 15 further comprising:
synchronizing, at the digital demodulator, with the tuner;
generating, at the digital demodulator, an ideal request size value based on the synchronizing with the tuner; and
generating, at the control loop, the target size value based at least in part on the ideal request size value.

17 . The method of claim 16 further comprising:
outputting, at a first combiner, a difference value between half of a size of the buffer and a current volume of samples in the buffer;
receiving, at a loop filter, the difference value from the first combiner and generate a delta value;
receiving, at a second combiner, the delta value from the loop filter and the ideal request size value from the digital demodulator; and
generating, at the second combiner, the target size value based on the delta value and the ideal request size value.

18 . The method of claim 15 wherein the receiver circuit includes an inter integrated circuit sound receiver.

19 . The method of claim 15 further comprising generating, at a clock generator, a demodulator clock, wherein the demodulator clock is asynchronous with a tuner clock of the tuner.

20 . The method of claim 15 wherein the sample rate converter, the buffer, the digital demodulator, and the control loop are implemented by a software function.

Assignees

• Skyworks Solutions Inc

Inventors

• Wallace Bradley Arthur
• Kleinerman Alexander

Classifications

• H04L27/2649 Primary

  Demodulators · CPC title

• H04B1/16 Primary

  Circuits · CPC title