Interface to provide selectable time domain or frequency domain information to downstream circuitry

Patent metadata

Field	Value
Publication number	US-10911289-B1
Application number	US-201916527571-A
Country	US
Kind code	B1
Filing date	Jul 31, 2019
Priority date	Jul 31, 2019
Publication date	Feb 2, 2021
Grant date	Feb 2, 2021

Abstract

In one embodiment, an apparatus includes first and second tuners to receive and process a radio frequency (RF) signal and output a first and second plurality of frequency domain sub-carriers. The apparatus may further include a combiner circuit to combine a first plurality of demodulated frequency domain sub-carriers and a second plurality of demodulated frequency domain sub-carriers into a plurality of combined frequency domain sub-carriers, and an output circuit coupled to the combiner circuit. In a first mode, the output circuit is to embed a format indicator with each of the plurality of combined frequency domain sub-carriers to indicate a frequency domain format, and to output the plurality of combined frequency domain sub-carriers with the embedded format indicator to a downstream processing circuit for channel decoding.

First claim

What is claimed is:

1. An apparatus comprising:
a first tuner comprising:
a first analog front end circuit to receive a radio frequency (RF) signal and downconvert the RF signal to a first lower frequency signal;
a first digitizer to digitize the first lower frequency signal into a first digitized first lower frequency signal;
a first fast Fourier transform (FFT) engine to compute a first plurality of frequency domain sub-carriers from the first digitized first lower frequency signal; and
a first format demodulator to demodulate the first plurality of frequency domain sub-carriers;

a second tuner comprising:
a second analog front end circuit to receive the RF signal and downconvert the RF signal to a second lower frequency signal;
a second digitizer to digitize the second lower frequency signal into a second digitized second lower frequency signal;
a second FFT engine to compute a second plurality of frequency domain sub-carriers from the second digitized second lower frequency signal; and
a second format demodulator to demodulate the second plurality of frequency domain sub-carriers;

a combiner circuit to combine the first plurality of demodulated frequency domain sub-carriers and the second plurality of demodulated frequency domain sub-carriers into a plurality of combined frequency domain sub-carriers; and
an output circuit coupled to the combiner circuit, wherein in a first mode, the output circuit is to embed a format indicator with each of the plurality of combined frequency domain sub-carriers to indicate a frequency domain format, and to output the plurality of combined frequency domain sub-carriers with the embedded format indicator to a downstream processing circuit for channel decoding.

2. The apparatus of claim 1 , further comprising a control circuit to control the output circuit to operate in the first mode and to operate in a second mode in which time domain signal information is sent to the downstream processing circuit.

3. The apparatus of claim 2 , wherein the control circuit is to control the output circuit to operate in one of the first mode and the second mode based on format information received from a host processor.

4. The apparatus of claim 2 , further comprising a frequency-to-time converter coupled to the combiner circuit, wherein in the second mode, the frequency-to-time converter is to convert the plurality of combined frequency domain sub-carriers into a plurality of combined time domain samples and provide the plurality of combined time domain samples to the output circuit.

5. The apparatus of claim 4 , wherein when the control circuit is to control the output circuit to operate in the first mode, the control circuit is to disable the frequency-to-time converter.

6. The apparatus of claim 2 , wherein in the first mode, the first format demodulator is to coherently demodulate the first plurality of frequency domain sub-carriers, and in the second mode the first format demodulator is to non-coherently demodulate the first plurality of frequency domain sub-carriers.

7. The apparatus of claim 2 , wherein the first tuner comprises an interface to couple to the downstream processing circuit, the interface having a plurality of lines including:
a first line to communicate a frame clock;
a second line to communicate a bit clock;
a third line to communicate first complex information with the embedded format indicator; and
a fourth line to communicate second complex information with the embedded format indicator.

8. The apparatus of claim 7 , wherein in the first mode the third line is to communicate the first complex information in the frequency domain and in the second mode the third line is to communicate the first complex information in the time domain.

9. The apparatus of claim 1 , further comprising a bypass path coupled between the combiner circuit and the output circuit, wherein in the first mode, the bypass path is to provide the plurality of combined frequency domain sub-carriers to the output circuit.

10. The apparatus of claim 1 , wherein the first tuner further comprises a first synchronizer to synchronize the first digitized first lower frequency signal and provide the synchronized first digitized first lower frequency signal to the first FFT engine.

11. The apparatus of claim 1 , wherein the output circuit is further to embed metadata associated with the RF signal into the plurality of combined frequency domain sub-carriers, the metadata comprising signal metric information regarding the RF signal.

12. A non-transitory computer readable medium comprising instructions that when executed enable a system to perform a method comprising:
in response to configuration information from a host processor for processing an incoming radio frequency (RF) signal of a first digital radio broadcast (DRB) format, configuring a multi-tuner integrated circuit (IC) for a first mode of operation in which the multi-tuner IC is to output frequency domain information to a coprocessor coupled to the multi-tuner IC;
receiving, in a first tuner of the multi-tuner IC, the incoming RF signal and processing the incoming RF signal into first frequency domain sample information comprising demodulated first frequency domain sub-carriers;
receiving, in a second tuner of the multi-tuner IC, the incoming RF signal and processing the incoming RF signal into second frequency domain sample information comprising demodulated second frequency domain sub-carriers;
thereafter combining the first frequency domain sample information and the second frequency domain sample information into combined frequency domain sample information;
embedding a format indicator into each of a plurality of sub-carriers of the combined frequency domain sample information to indicate a frequency domain format; and
outputting the plurality of sub-carriers of the combined frequency domain sample information having the embedded format indicator from the multi-tuner IC to the coprocessor.

13. The non-transitory computer readable medium of claim 12 , wherein the method further comprises, in the first mode of operation, disabling a frequency-to-time converter of the multi-tuner IC.

14. The non-transitory computer readable medium of claim 13 , wherein the method further comprises, in a second mode of operation, enabling the frequency-to-time converter and converting the plurality of sub-carriers of the combined frequency domain sample information into a plurality of time domain samples.

15. The non-transitory computer readable medium of claim 14 , wherein the method further comprises:
embedding another format indicator into the plurality of time domain samples to indicate a time domain format; and
outputting the plurality of time domain samples having the embedded another format indicator from the multi-tuner IC to the coprocessor.

16. The non-transitory computer readable medium of claim 12 , wherein processing the incoming RF signal into the first frequency domain sample information comprises performing coherent demodulation to obtain the demodulated first frequency domain sub-carriers and the second frequency domain sub-carriers.

17. The non-transitory computer readable medium of claim 12 , wherein the method further comprises embedding signal metric information regarding the incoming RF signal into at least some of the plurality of sub-carriers of the combined frequency domain sample information.

18. A system comprising:
a first integrated circuit comprising a plurality of tuners to receive, downconvert and digitize an incoming radio frequency (RF) signal into a fi

Assignees

• Silicon Lab Inc

Inventors

• Strickland Ken
• Wallace Bradley Arthur
• Alelyunas Carl
• Mesarovic Vladimir

Classifications

• H04L27/2649 Primary

  Demodulators · CPC title

• H04B7/0857

  using maximum ratio combining techniques, e.g. signal-to- interference ratio [SIR], received signal strenght indication [RSS] · CPC title

• H04L25/03159

  operating in the frequency domain (H04L25/03165, H04L25/03178 take precedence) · CPC title

• H04L27/14

  Demodulator circuits; Receiver circuits · CPC title

• H04L27/2666

  Acquisition of further OFDM parameters, e.g. bandwidth, subcarrier spacing, or guard interval length · CPC title