Power management chip and operating method for supporting multimode operations

Patent metadata

Field	Value
Publication number	US-12542487-B2
Application number	US-202318188157-A
Country	US
Kind code	B2
Filing date	Mar 22, 2023
Priority date	Aug 25, 2022
Publication date	Feb 3, 2026
Grant date	Feb 3, 2026

Abstract

A power management chip includes a gate driver configured to output a first gate signal driving a first power switch and a second gate signal driving the second power switch, a multiplexer configured to receive an error detect signal from a first error amplifier and a first gate signal from the gate driver, and drive the first power switch with either of the error detect signal or the first gate signal in response to a mode select signal; an inductor detection logic configured to receive the inductor detect signal, output a comparison detect signal and a pulse signal for detecting an external inductor, and output the mode select signal corresponding to a result of the detecting, and a comparator comparing an internal output voltage of an output node and an output voltage of the feedback node in response to the comparison detect signal.

First claim

What is claimed is:

1 . A power management chip comprising:
a first power switch connected between a power terminal and an output node; a second power switch connected between the output node and a ground terminal; a first error amplifier configured to compare a feedback node and a reference voltage when a mode select signal is a first logic level; a second error amplifier configured to compare the feedback node and the reference voltage when the mode select signal is a second logic level different from the first logic level; a pulse width modulation logic configured to receive an output of the second error amplifier to output a drive signal; a gate driver configured to receive an inductor detect signal and the mode select signal, receive the drive signal from the pulse width modulation logic, and to output a first gate signal driving a first power switch and a second gate signal driving a second power switch; a multiplexer configured to receive an error detect signal from the first error amplifier and the first gate signal from the gate driver, and to drive the first power switch with one of the error detect signal and the first gate signal in response to the mode select signal; an inductor detection logic configured to receive the inductor detect signal, to output a comparison detect signal and a pulse signal for determining whether an external inductor is present, and to output the mode select signal corresponding to a result of the determining; and a comparator configured to compare an internal output voltage of the output node and an output voltage of the feedback node in response to the comparison detect signal.

2 . The power management chip of claim 1 , further comprising a flow switch configured to receive the pulse signal and connected between the output node and the feedback node.

3 . The power management chip of claim 1 , further comprising a feedback network circuit connected to the feedback node and configured to output a voltage of the feedback node to the first error amplifier and the second error amplifier.

4 . The power management chip of claim 1 , wherein the gate driver comprises:
at least one switch configured to float an output according to the mode select signal; and two multiplexers configured to receive the drive signal and the pulse signal for an inductor presence detection mode and an inductor absence detection mode.

5 . The power management chip of claim 1 , wherein the inductor detection logic outputs the pulse signal for driving an inductor both end switch externally, and outputs the mode select signal in response to an output of the comparator.

6 . The power management chip of claim 1 , wherein the multiplexer is connected to the feedback node to reduce a leakage current, when operating in a low drop out (LDO) mode.

7 . The power management chip of claim 1 , further comprising a sleep LDO for soft start-up, when driving in a buck mode, and connected to the feedback node.

8 . The power management chip of claim 7 , wherein the sleep LDO is configured to perform a start-up operation in which an output voltage of the sleep LDO rises to be equal to or higher than a predetermined voltage, when a power voltage rises.

9 . The power management chip of claim 1 , wherein, when the mode select signal indicates a buck mode, and transitions from an active mode to a power-down mode, an inductor both end switch is short-circuited.

10 . The power management chip of claim 1 , wherein the mode select signal indicates one of a low drop out (LDO) mode or a buck mode.

11 . A method of operating a power management chip for supporting multimode operations, comprising:
detecting a presence of an external inductor; and selecting one of a low drop out (LDO) mode or a buck mode based on a result of the detecting, wherein the detecting the presence of the external inductor comprises: operating a flow switch to short a circuit between an output node and a feedback node in response to a pulse signal; and comparing an internal output voltage of the output node and an output voltage of the feedback node.

12 . The method of claim 11 , further comprising:
outputting an error amplification signal by comparing a reference voltage and a voltage of the feedback node in response to a mode select signal, when the external inductor is not present; selecting the error amplification signal from a first gate signal and the error amplification signal in response to the mode select signal in a multiplexer; and driving a first power switch according to the error amplification signal.

13 . The method of claim 11 , further comprising:
outputting an error amplification signal by comparing a reference voltage and a voltage of the feedback node in response to an inverted mode select signal, when the external inductor is present; outputting a drive signal corresponding to the error amplification signal in a pulse width modulation logic; outputting a first gate signal and a second gate signal corresponding to the drive signal in response to the inverted mode select signal in a gate driver; selecting the first gate signal from the first gate signal and the error amplification signal in response to the inverted mode select signal in a multiplexer; and driving a first power switch according to the first gate signal.

14 . The method of claim 13 , further comprising driving a second power switch in response to the second gate signal.

15 . The method of claim 11 , further comprising connecting a multiplexer to the feedback node to reduce a leakage current, when the external inductor is present.

16 . A method of operating a power management chip for determining one of a low drop out (LDO) mode and a buck mode depending on whether an inductor is detected, comprising:
starting up the buck mode using a sleep LDO; and reducing overshoot of an output voltage by operating a flow switch to short a circuit between an output node and a feedback node, when transitioning from an active mode to a power-down mode.

17 . The method of claim 16 , further comprising turning off the sleep LDO after the starting up has completed.

18 . The method of claim 16 , further comprising detecting a presence or absence of the inductor.

19 . The method of claim 18 , wherein the power management chip comprises a multiplexer for driving a power switch according to a mode selected from the LDO mode and the buck mode, and
the method further comprises connecting the multiplexer to the feedback node, when the inductor is not present.

20 . The method of claim 16 , further comprising turning off components corresponding to a mode not selected from the LDO mode and the buck mode.

21 . A method of operating a power management chip for supporting multimode operations, comprising:
detecting a presence of an external inductor; and selecting one of a low drop out (LDO) mode or a buck mode based on a result of the detecting, wherein the detecting the presence of the external inductor comprises: receiving an inductor detect signal; outputting a comparison detect signal and a pulse signal for determining whether the external inductor is present; outputting a mode select signal corresponding to a result of the determining; and comparing an internal output voltage of an output node and an output voltage of a feedback node in response to the comparison detect signal.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Gwon Huidong
• Kong Taehwang
• Kim Minjae
• Yang Junhyeok
• Lee Yunho

Classifications

• H02M1/36

  Means for starting or stopping converters · CPC title

• H02M1/0045 Primary

  Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode · CPC title

• H02M1/0032

  Control circuits allowing low power mode operation, e.g. in standby mode · CPC title

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title