Method for producing aluminum nitride substrate, aluminum nitride substrate, and method for suppressing occurrence of cracks in aluminum nitride layer
US-2023197486-A1 · Jun 22, 2023 · US
Method for manufacturing a semiconductor substrate and method for suppressing occurrence of cracks in a growth layer
US12540416B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12540416-B2 |
| Application number | US-202117996091-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 30, 2021 |
| Priority date | Apr 14, 2020 |
| Publication date | Feb 3, 2026 |
| Grant date | Feb 3, 2026 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
An object of the present invention is to provide a novel technique capable of suppressing the occurrence of cracks in the growth layer. The present invention is a method for manufacturing a semiconductor substrate, which includes: an embrittlement processing step S 10 of reducing strength of an underlying substrate 10 ; and a crystal growth step S 20 of forming the growth layer 20 on the underlying substrate 10 . In addition, the present invention is a method for suppressing the occurrence of cracks in the growth layer 20 , and this method includes an embrittlement processing step S 10 of reducing the strength of the underlying substrate 10 before forming the growth layer 20 on the underlying substrate 10.
First claim
Opening claim text (preview).
The invention claimed is: 1 . A method for manufacturing a semiconductor substrate, comprising: an embrittlement processing step of reducing strength of an underlying substrate; and a crystal growth step of forming a growth layer on the underlying substrate, wherein the embrittlement processing step includes a through hole formation step of forming through holes in the underlying substrate; wherein the underlying substrate is freestanding and the through holes allow airflow to pass through the underlying substrate; wherein a ratio of an area occupied by the through holes to a surface of the underlying substrate on which the growth layer is formed is 50% or more; and wherein the crystal growth step is a step of forming the growth layer having a shrinkage rate different from that of the underlying substrate. 2 . The method for manufacturing a semiconductor substrate according to claim 1 , wherein the underlying substrate and the growth layer have different doping concentrations. 3 . The method for manufacturing a semiconductor substrate according to claim 1 , wherein the underlying substrate and the growth layer are made of different materials. 4 . The method for manufacturing a semiconductor substrate according to claim 1 , wherein the embrittlement processing step includes a strained layer removal step of removing a strained layer introduced in the through hole formation step. 5 . The method for manufacturing a semiconductor substrate according to claim 4 , wherein the through hole formation step is a step of forming the through holes by irradiating the underlying substrate with a laser. 6 . The method for manufacturing a semiconductor substrate according to claim 4 , wherein the strained layer removal step is a step of removing a strained layer of the underlying substrate by heat treatment. 7 . The method for manufacturing a semiconductor substrate according to claim 4 , wherein the underlying substrate is silicon carbide, and the strained layer removal step is a step of etching the underlying substrate under a silicon atmosphere. 8 . The method for manufacturing a semiconductor substrate according to claim 1 , wherein the crystal growth step is a step of growing via a physical vapor transport method. 9 . A method for suppressing occurrence of cracks in a growth layer, comprising an embrittlement processing step of reducing strength of an underlying substrate before forming the growth layer having a shrinkage rate different from that of the underlying substrate on the underlying substrate, wherein the embrittlement processing step includes a through hole formation step of forming through holes in the underlying substrate; wherein the underlying substrate is freestanding and the through holes allow airflow to pass through the underlying substrate; and wherein a ratio of an area occupied by the through holes to a surface of the underlying substrate on which the growth layer is formed is 50% or more. 10 . The method according to claim 9 , wherein the embrittlement processing step includes a strained layer removal step of removing a strained layer introduced in the through hole formation step. 11 . The method according to claim 10 , wherein the strained layer removal step is a step of etching the underlying substrate by heat treatment. 12 . The method according to claim 10 , wherein the underlying substrate is silicon carbide, and the strained layer removal step is a step of etching the underlying substrate under a silicon atmosphere.
Assignees
Inventors
Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
AIII-nitrides · CPC title
Patent family
Related publications grouped by family.
External sources
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US12540416B2 cover?
- An object of the present invention is to provide a novel technique capable of suppressing the occurrence of cracks in the growth layer. The present invention is a method for manufacturing a semiconductor substrate, which includes: an embrittlement processing step S 10 of reducing strength of an underlying substrate 10 ; and a crystal growth step S 20 of forming the growth layer 20 on…
- Who is the assignee on this patent?
- Kwansei Gakuin Educational Found, Toyota Tsusho Corp
- What technology area does this patent fall under?
- Primary CPC classification C30B23/025. Mapped technology areas include Chemistry & Metallurgy.
- When was this patent published?
- Publication date Tue Feb 03 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).