Seal ring structure in the peripheral of device dies and with zigzag patterns and method forming same

US12538836B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12538836-B2
Application numberUS-202418767481-A
CountryUS
Kind codeB2
Filing dateJul 9, 2024
Priority dateAug 27, 2021
Publication dateJan 27, 2026
Grant dateJan 27, 2026

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method includes forming a plurality of dielectric layers, forming a lower portion of a seal ring including a plurality of metal layers, each extending into one of the plurality of dielectric layers, depositing a first passivation layer over the plurality of dielectric layers, forming an opening in the first passivation layer, forming a via ring in the opening and physically contacting the lower portion of the seal ring, and forming a metal ring over the first passivation layer and joined to the via ring. The via ring and the metal ring form an upper portion of the seal ring. The metal ring includes an edge portion having a zigzag pattern. The method further includes forming a second passivation layer on the metal ring, and performing a singulation process to form a device die, with the seal ring being proximate edges of the device die.

First claim

Opening claim text (preview).

What is claimed is: 1 . A structure comprising: a die comprising: a substrate; a plurality of dielectric layers over the substrate; a first passivation layer over the plurality of dielectric layers; a seal ring comprising: a plurality of conductive rings, each extending into one of the plurality of dielectric layers; a via ring extending into the first passivation layer and physically contacting a top conductive ring in the plurality of conductive rings; and a metal ring over the first passivation layer and joined to the via ring, wherein the metal ring comprises a first edge portion having a zigzag pattern, wherein the first edge portion is adjacent to an edge of the die; and a second passivation layer over the metal ring. 2 . The structure of claim 1 , wherein the first edge portion comprises a plurality of repeating units, with each of the repeating units comprising a first section and a second section having lengthwise directions parallel to the edge of the die, with the first section and the second section having different distance values from the edge of the die. 3 . The structure of claim 2 , wherein the each of the repeating units further comprises an interconnection section interconnecting the first section and the second section. 4 . The structure of claim 2 , wherein each of the plurality of repeating units has a pitch smaller than about 90 μm. 5 . The structure of claim 1 , wherein the via ring comprises a second edge portion underlying and overlapped by the first edge portion of the metal ring, and the second edge portion of the via ring is straight. 6 . The structure of claim 5 , wherein in a top view of the structure, the first edge portion of the metal ring swings relative to the second edge portion of the via ring. 7 . The structure of claim 6 , wherein in the top view, the first edge portion comprises: a first section having a first middle line on a first side of a second middle line of the second edge portion of the via ring; and a second section having a third middle line on a second side of the second middle line opposite to the first side. 8 . The structure of claim 6 , wherein in the top view, the first edge portion comprises: a first section having a first middle line on a side of a second middle line of the second edge portion of the via ring; and a second section having a third middle aligned to the second middle line. 9 . The structure of claim 1 , wherein the metal ring further comprises: a second edge portion having an additional zigzag pattern; and a corner portion interconnecting the first edge portion and the second edge portion, wherein the corner portion is straight. 10 . The structure of claim 1 further comprising a polymer layer over and contacting the second passivation layer. 11 . A structure comprising: a die comprising: a first edge and a second edge joined to each other at a corner of the die; a metal ring comprising: a first edge portion and a second edge portion proximate the first edge and the second edge, respectively, wherein the first edge portion comprises: a first section parallel to the first edge, wherein the first section is spaced apart from the first edge by a first distance; a second section parallel to the first edge, wherein the second section is spaced apart from the first edge by a second distance different from the first distance; and an interconnection section interconnecting, and physically joining, the first section and the second section; and a via ring comprising a third section and a fourth section underlying and physically joined to the first section and the second section, respectively. 12 . The structure of claim 11 , wherein the first section, the second section, and the interconnection section form a repeating unit, and wherein the first edge portion comprises a plurality of additional repeating units. 13 . The structure of claim 12 , wherein the plurality of additional repeating units are identical to the repeating unit. 14 . The structure of claim 11 , wherein the third section and the fourth section are joined with each other to form a straight continuous section. 15 . The structure of claim 11 , wherein in a top view of the structure, the first section has a first lengthwise direction, and the interconnection section has a second lengthwise direction, and wherein an angle between the first lengthwise direction and the second lengthwise direction is greater than 0 degrees and smaller than about 90 degrees. 16 . A structure comprising: a semiconductor substrate comprising a plurality of edges connected to form a rectangle in a top view of the structure; a via ring over the semiconductor substrate, wherein the via ring comprises a first plurality of edge portions parallel to respective ones of the plurality of edges of the semiconductor substrate; and a metal ring over and contacting the via ring, wherein the metal ring comprises a second plurality of edge portions, and wherein one of the second plurality of edge portions comprises: a first portion parallel to one of the plurality of edges of the semiconductor substrate; and a second portion forming an angle with the first portion in the top view of the structure, wherein the angle is greater than zero degree and smaller than 90 degrees. 17 . The structure of claim 16 , wherein the one of the second plurality of edge portions further comprises a third portion parallel to the first portion, wherein the second portion is between, and is physically joined to, the first portion and the third portion. 18 . The structure of claim 17 , wherein a first middle line of the first portion in a lengthwise direction of the first portion is aligned to a first straight line, and a second middle line of the third portion in a lengthwise direction of the third portion is aligned to a second straight line, and the second straight line is parallel to, and is offset from, the first straight line. 19 . The structure of claim 17 , wherein the first portion, the second portion, and the third portion are joined to form a repeating unit, and the one of the second plurality of edge portions comprises a plurality of repeating units identical to the repeating unit. 20 . The structure of claim 16 , wherein the angle is between about 30 degrees and about 60 degrees.

Assignees

Inventors

Classifications

  • Electricity · mapped topic

  • Electricity · mapped topic

  • Electricity · mapped topic

  • H01L23/10Primary

    Electricity · mapped topic

  • the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

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What does patent US12538836B2 cover?
A method includes forming a plurality of dielectric layers, forming a lower portion of a seal ring including a plurality of metal layers, each extending into one of the plurality of dielectric layers, depositing a first passivation layer over the plurality of dielectric layers, forming an opening in the first passivation layer, forming a via ring in the opening and physically contacting the low…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H01L23/10. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 27 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).