Semiconductor device

Patent metadata

Field	Value
Publication number	US-9230920-B2
Application number	US-201514626331-A
Country	US
Kind code	B2
Filing date	Feb 19, 2015
Priority date	Feb 26, 2013
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

To improve reliability of a semiconductor device obtained through a dicing step. In a ring region, a first outer ring is provided outside a seal ring, and a second outer ring is provided outside the first outer ring. This can prevent a crack from reaching even the seal ring that exists in the ring region, for example, when a scribe region located outside the ring region is cut off by a dicing blade.

First claim

What is claimed is:

1. A semiconductor device comprising:
(a) a semiconductor substrate including a circuit region in which an integrated circuit is formed;
(b) a seal ring formed over the semiconductor substrate so as to surround the integrated circuit in plan view, the seal ring formed of a first set of multi-layered metal patterns and an additional metal pattern formed on the first set of multi-layered metal patterns, the additional metal pattern being an uppermost pattern of the seal ring;
(c) a first insulating film formed over the semiconductor substrate so as to cover the uppermost pattern of the seal ring; and
(d) a first outer ring formed over the semiconductor substrate so as to surround the seal ring in plan view, the first outer ring formed of a second set of multi-layered metal patterns,
wherein a lowermost pattern of the first set of multi-layered metal patterns is electrically coupled with the semiconductor substrate,
wherein a lowermost pattern of the second set of multi-layered metal patterns is not electrically coupled with the semiconductor substrate,
wherein the first insulating film has a first edge in an outer region of the seal ring,
wherein the first outer ring is positioned on an outer side than the first edge, and
wherein an uppermost pattern of the second set of multi-layered metal patterns is positioned in a position lower than the uppermost pattern of the seal ring in a thickness direction of the semiconductor substrate.

2. The semiconductor device according to claim 1 , further comprising a field insulating film formed on the semiconductor substrate,
wherein the first outer ring is arranged above the field insulating film in plan view.

3. A semiconductor device comprising:
(a) a semiconductor substrate including a circuit region in which an integrated circuit is formed;
(b) a seal ring formed over the semiconductor substrate so as to surround the integrated circuit in plan view, the seal ring formed of a first set of multi-layered metal patterns;
(c) a first insulating film formed over the semiconductor substrate so as to cover an uppermost pattern of the first set of multi-layered metal patterns; and
(d) a first outer ring formed over the semiconductor substrate so as to surround the seal ring in plan view, the first outer ring formed of a second set of multi-layered metal patterns,
wherein a lowermost pattern of the first set of multi-layered metal patterns is electrically coupled with the semiconductor substrate,
wherein a lowermost pattern of the second set of multi-layered metal patterns is not electrically coupled with the semiconductor substrate,
wherein the first insulating film has a first edge in an outer region of the seal ring,
wherein the first outer ring is positioned on an outer side than the first edge,
wherein an uppermost pattern of the second set of multi-layered metal patterns is positioned in a position lower than the uppermost pattern of the first set of multi-layered metal patterns in a thickness direction of the semiconductor substrate,
wherein the first insulating film includes a slit surrounding the first outer ring in plan view, and
wherein the slit is defined by the first edge of the first insulating film and a second edge of the first insulating film positioned on an opposite side of the first edge of the first insulting film.

4. A semiconductor device comprising:
(a) a semiconductor substrate including a circuit region in which an integrated circuit is formed;
(b) a seal ring formed over the semiconductor substrate so as to surround the integrated circuit in plan view, the seal ring formed of a first set of multi-layered metal patterns;
(c) a first insulating film formed over the semiconductor substrate so as to cover an uppermost pattern of the first set of multi-layered metal patterns;
(d) a first outer ring formed over the semiconductor substrate so as to surround the seal ring in plan view, the first outer ring formed of a second set of multi-layered metal patterns; and
(e) a second outer ring formed over the semiconductor substrate,
wherein a lowermost pattern of the first set of multi-layered metal patterns is electrically coupled with the semiconductor substrate,
wherein a lowermost pattern of the second set of multi-layered metal patterns is not electrically coupled with the semiconductor substrate,
wherein the first insulating film has a first edge in an outer region of the seal ring,
wherein the first outer ring is positioned on an outer side than the first edge,
wherein an uppermost pattern of the second set of multi-layered metal patterns is positioned in a position lower than the uppermost pattern of the first set of multi-layered metal patterns in a thickness direction of the semiconductor substrate,
wherein the second outer ring is formed of a third set of multi-layered metal patterns and positioned between the seal ring and the first outer ring in plan view,
wherein an uppermost pattern of the third set of multi-layered metal patterns is positioned in a position lower than the uppermost pattern of the first set of multi-layered metal patterns in the thickness direction of the semiconductor substrate,
wherein the uppermost pattern of the third set of multi-layered metal patterns is positioned in a position higher than the uppermost pattern of the second set of multi-layered metal patterns in the thickness direction of the semiconductor substrate, and
wherein a lowermost pattern of the third set of multi-layered metal patterns is not electrically coupled with the semiconductor substrate.

5. The semiconductor device according to claim 4 ,
wherein the second outer ring is positioned on an inner side than the first edge.

6. The semiconductor device according to claim 4 , further comprising a field insulating film formed on the semiconductor substrate,
wherein the second outer ring is arranged above the field insulating film in plan view.

7. A semiconductor device comprising:
(a) a semiconductor substrate including a circuit region in which an integrated circuit is formed;
(b) a seal ring formed over the semiconductor substrate so as to surround the integrated circuit in plan view, the seal ring formed of a first set of multi-layered metal patterns;
(c) a first insulating film formed over the semiconductor substrate so as to cover an uppermost pattern of the first set of multi-layered metal patterns; and
(d) a first outer ring formed over the semiconductor substrate so as to surround the seal ring in plan view, the first outer ring formed of a second set of multi-layered metal patterns,
wherein a lowermost pattern of the first set of multi-layered metal patterns is electrically coupled with the semiconductor substrate,
wherein a lowermost pattern of the second set of multi-layered metal patterns is not electrically coupled with the semiconductor substrate,
wherein the first insulating film has a first edge in an outer region outside of the seal ring,
wherein the first outer ring is positioned on an outer side than the first edge, and
wherein an uppermost pattern of the second set of multi-layered metal patterns is positioned in a position lower than the uppermost pattern of the first set of multi-layered metal patterns in a thickness direction of the semiconductor substrate.

8. The semiconductor substrate according to claim 7 , wherein the first insulating film entirely covers an uppermost pattern of the first set of multi-layered metal patterns.

Assignees

• Renesas Electronics Corp

Inventors

• Ishii Yasushi

Classifications

• H10W72/9232

  with additional elements interposed between layers · CPC title

• H10W72/983

  Reinforcing structures, e.g. collars · CPC title

• H10W72/934

  Cross-sectional shape, i.e. in side view · CPC title

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10W42/00 Primary

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title