Integrated chip package including a crack-resistant lid structure and methods of forming the same

Patent metadata

Field	Value
Publication number	US-12538835-B2
Application number	US-202217898834-A
Country	US
Kind code	B2
Filing date	Aug 30, 2022
Priority date	May 26, 2022
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

A chip package structure includes an assembly containing an interposer and semiconductor dies; a packaging substrate attached to the assembly through solder material portions; and a lid structure attached to the packaging substrate. The lid structure includes: a first plate portion having a first thickness and located in an interposer-projection region having an areal overlap with the interposer in a plan view; a second plate portion having a second thickness that is less than the first thickness, laterally surrounding, and adjoined to, the first plate portion, and located outside the interposer-projection region; and a plurality of foot portions adjoined to the second plate portion, laterally spaced from the first plate portion, and attached to a respective top surface segment of the packaging substrate through a respective adhesive portion.

First claim

What is claimed is:

1 . A chip package structure comprising:
an assembly comprising an interposer and semiconductor dies; a packaging substrate attached to the assembly through solder material portions; and a lid structure attached to the packaging substrate and comprising: a first plate portion having a first thickness and located in an interposer-projection region having an areal overlap with the interposer in a plan view; a second plate portion having a second thickness that is less than the first thickness, laterally surrounding, and adjoined to, the first plate portion, and located outside the interposer-projection region; and a plurality of foot portions adjoined to the second plate portion, laterally spaced from the first plate portion, and attached to a respective top surface segment of the packaging substrate through a respective adhesive portion, wherein the second plate portion comprises four channel segments that are located between the first plate portion and a respective one of the plurality of foot portions.

2 . The chip package structure of claim 1 , wherein:
each of the plurality of foot portions laterally extends along a respective lateral direction that is parallel to one of sidewalls of the lid structure, and has a respective foot length along the respective lateral direction; and the respective foot length is less than a maximum lateral dimension of the first plate portion along the respective lateral direction.

3 . The chip package structure of claim 1 , wherein each of the four channel segments has a uniform channel width along a direction of a lateral spacing between the first plate portion and a most proximal one of the foot portions.

4 . The chip package structure of claim 1 , wherein:
the second plate portion comprises four corner plate portion segments that are adjoined to the four channel segments; and each of the plurality of foot portions has a respective foot length along a horizontal direction that is perpendicular to a direction of separation from the first plate portion, and has a respective foot width along another horizontal direction that is parallel to the direction of separation from the first plate portion.

5 . The chip package structure of claim 4 , wherein:
each of the four corner plate portion segments has a respective first lateral dimension along a first horizontal direction and a respective second lateral dimension along a second horizontal direction; and each of the first lateral dimensions and the second lateral dimensions is greater than any of the foot widths of the foot portions.

6 . The chip package structure of claim 4 , wherein the four corner plate portion segments of the second plate portion are adjoined to a respective pair of two outmost sidewalls of the lid structure.

7 . The chip package structure of claim 4 , wherein the four corner plate portion segments of the second plate portion are laterally spaced from outermost sidewalls of the lid structure by a respective rim portion of the lid structure having a same vertical extent as the foot portions.

8 . The chip package structure of claim 1 , wherein each of the foot portions comprises a respective lengthwise sidewall that has:
a top edge that is adjoined to the second plate portion within a horizontal plane that overlies a horizontal plane including a bottom surface of the first plate portion; and a bottom edge located within another horizontal plane that underlies a bottommost surface of the assembly.

9 . The chip package structure of claim 1 , further comprising a thermal interface material (TIM) layer located between, and contacting, a top surface of the assembly and a bottom surface of the first plate portion.

10 . The chip package structure of claim 1 , further comprising an intra-lid cavity laterally surrounding the first plate portion and the assembly, and laterally surrounded by the foot portions, wherein the intra-lid cavity is connected to an ambient located outside outmost sidewalls of the lid structure through a plurality of openings located between the foot portions.

11 . The chip package structure of claim 1 , further comprising an intra-lid cavity laterally surrounding the first plate portion and the assembly, and laterally surrounded by the foot portions, wherein the intra-lid cavity is encapsulated within the lid structure, and is disconnected from an ambient located outside outmost sidewalls of the lid structure by a combination of the foot portions and rim portions of the lid structure that connect the foot portions and having a lesser lateral thickness than the foot portions.

12 . A chip package structure comprising:
an assembly comprising an interposer and semiconductor dies; a packaging substrate attached to the assembly through solder material portions; and a lid structure attached to the packaging substrate and comprising: a first plate portion having a first thickness and located in an interposer-projection region having a same area as the interposer in a plan view; a second plate portion having a second thickness that is less than the first thickness, laterally surrounding, and adjoined to, the first plate portion, and located outside the interposer-projection region; and a plurality of foot portions adjoined to the second plate portion, wherein top surfaces of the first plate portion, the second plate portion, and the plurality of foot portions are located within a same horizontal plane, and wherein each of the plurality of foot portions has a respective lengthwise sidewall that is parallel to a respective sidewall of the first plate portion, has a lesser lateral thickness than the respective sidewall of the first plate portion, and is laterally spaced from the respective sidewall of the first plate portion by a respective uniform spacing that equals a width of a respective channel segment of the second plate portion.

13 . The chip package structure of claim 12 , wherein:
the second plate portion comprises four corner plate portion segments that are adjoined to the four channel segments; and each of the plurality of foot portions has a respective foot length along a horizontal direction that is perpendicular to a direction of separation from the first plate portion, and has a respective foot width along another horizontal direction that is parallel to the direction of separation from the first plate portion.

14 . The chip package structure of claim 12 , further comprising an intra-lid cavity laterally surrounding the first plate portion and the assembly, and laterally surrounded by the foot portions, wherein the intra-lid cavity is connected to an ambient located outside outmost sidewalls of the lid structure through a plurality of openings located between the foot portions.

15 . The chip package structure of claim 12 , further comprising an intra-lid cavity laterally surrounding the first plate portion and the assembly, and laterally surrounded by the foot portions, wherein the intra-lid cavity is encapsulated within the lid structure, and is disconnected from an ambient located outside outmost sidewalls of the lid structure by a combination of the foot portions and rim portions of the lid structure that connect the foot portions and having a lesser lateral thickness than the foot portions.

16 . A method of forming a chip package structure, the method comprising:
providing an assembly comprising an interposer and semiconductor dies; attaching the assembly to a packaging substrate using solder material portions; providing a lid structure that comprises a first plate portion having a first thickness, a s

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hung Wensen
• Chen Tsung-Yu
• Shih Hsuan-Ning
• Wei Wen-Hsin

Classifications

• H01L2224/8385

  Electricity · mapped topic

• H01L2224/32245

  Electricity · mapped topic

• H01L2224/29386

  Electricity · mapped topic

• H01L2224/29347

  Electricity · mapped topic

• H01L2224/29339

  Electricity · mapped topic