Interconnect layer and method for manufacturing the same
US-2024420994-A1 · Dec 19, 2024 · US
US12538778B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12538778-B2 |
| Application number | US-202318228846-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 1, 2023 |
| Priority date | Aug 1, 2023 |
| Publication date | Jan 27, 2026 |
| Grant date | Jan 27, 2026 |
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A method includes obtaining a base structure including a stack of dielectric layers disposed on a substrate. The stack of dielectric layers includes a first photosensitive dielectric layer including a first photosensitive dielectric material sensitive to a first radiation dose, a second photosensitive dielectric layer including a second photosensitive dielectric material sensitive to a second radiation dose different from the first radiation dose, and a barrier layer disposed between the first photosensitive dielectric layer and the second photosensitive dielectric layer. The method further includes forming a dual damascene structure from the base structure using a dual damascene process.
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What is claimed is: 1 . A method comprising: obtaining a base structure comprising a stack of dielectric layers disposed on a substrate, the stack of dielectric layers comprising a first photosensitive dielectric layer comprising a first photosensitive dielectric material sensitive to a first radiation dose, a second photosensitive dielectric layer comprising a second photosensitive dielectric material sensitive to a second radiation dose different from the first radiation dose, and a barrier layer disposed between the first photosensitive dielectric layer and the second photosensitive dielectric layer; and forming a dual damascene structure from the base structure using a dual damascene process. 2 . The method of claim 1 , wherein the first photosensitive dielectric layer and the second photosensitive dielectric layer each comprise a respective photosensitive polyimide material. 3 . The method of claim 1 , wherein the first photosensitive dielectric layer and the second photosensitive dielectric layer each comprise a respective photoresist. 4 . The method of claim 1 , wherein the base structure further comprises an additional dielectric layer disposed between the first photosensitive dielectric layer and the substrate, and wherein the additional dielectric layer comprises a polyimide material. 5 . The method of claim 1 , wherein obtaining the base structure further comprises forming at least one of the first photosensitive dielectric layer or the second photosensitive dielectric layer using a spin-on deposition process. 6 . The method of claim 1 , wherein the barrier layer comprises aluminum oxide (Al 2 O 3 ). 7 . The method of claim 1 , wherein the barrier layer comprises hydrogen silsesquioxane (HSQ). 8 . The method of claim 1 , wherein the barrier layer comprises a self-assembled monolayer. 9 . The method of claim 1 , wherein obtaining the base structure further comprises: forming the barrier layer on the first photosensitive dielectric layer; and forming the second photosensitive dielectric layer on the barrier layer. 10 . The method of claim 9 , wherein forming the barrier layer comprises using a thermal atomic layer deposition process. 11 . The method of claim 9 , wherein forming the barrier layer comprises using a sputter deposition process. 12 . The method of claim 9 , wherein forming the barrier layer comprises using a spin-on deposition process. 13 . The method of claim 1 , wherein forming the dual damascene structure further comprises: exposing a first region of the base structure to the first radiation dose to obtain a first exposed region of the first photosensitive dielectric layer; exposing a second region of the base structure to the second radiation dose to obtain a second exposed region of the second photosensitive dielectric layer; developing the first photosensitive dielectric layer and the second photosensitive dielectric layer using at least one developer solution to form an opening by removing the first exposed region and the second exposed region; and forming conductive material within the opening to simultaneously form a conductive line and a via. 14 . The method of claim 13 , wherein the at least one developer solution removes a portion of the barrier layer to form the opening. 15 . The method of claim 13 , wherein forming the dual damascene structure further comprises performing an etch process to remove a portion of the barrier layer to form the opening. 16 . A device comprising: a substrate; a first photosensitive dielectric layer disposed on the substrate, the first photosensitive dielectric layer comprising a first photosensitive dielectric material sensitive to a first radiation dose; a barrier layer disposed on the first photosensitive dielectric layer; a second photosensitive dielectric layer disposed on the barrier layer, the second photosensitive dielectric layer comprising a second photosensitive dielectric material sensitive to a second radiation dose different from the first radiation dose; and conductive material disposed within the first photosensitive dielectric layer and the second photosensitive dielectric layer, the conductive material forming a conductive line and a via. 17 . The device of claim 16 , wherein the first photosensitive dielectric layer and the second photosensitive dielectric layer each comprise a respective photosensitive polyimide material. 18 . The device of claim 16 , wherein the first photosensitive dielectric layer and the second photosensitive dielectric layer each comprise a respective photoresist. 19 . The device of claim 16 , wherein the barrier layer comprises one of: aluminum oxide (Al 2 O 3 ), hydrogen silsesquioxane (HSQ), or a self-assembled monolayer. 20 . The device of claim 16 , further comprising an additional dielectric layer comprising a polyimide disposed on the substrate, wherein the first photosensitive dielectric layer and the conductive material are disposed on the additional dielectric layer.
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title
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