Successive approximation analog-to-digital conversion device skipping comparison results and its operating method

Patent metadata

Field	Value
Publication number	US-12537539-B2
Application number	US-202318471437-A
Country	US
Kind code	B2
Filing date	Sep 21, 2023
Priority date	Apr 6, 2023
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

The analog-to-digital conversion device includes a signal generating unit that generates a plurality of comparison voltages based on an analog input voltage and generates a plurality of comparison results of the plurality of comparison voltages based on a sampling period, a calculation unit that skips a comparison result generated by a comparison voltage having a smallest difference between the analog input voltages among the plurality of comparison voltages from the plurality of comparison results and generates an end of comparison based on a remaining plurality of comparison results, and a SAR logic unit that generates a digital signal corresponding to the end of comparison and stores information for each bit of the digital signal.

First claim

What is claimed is:

1 . An analog-to-digital conversion device comprising:
a signal generating unit configured to generate a plurality of comparison voltages based on an analog input voltage and to generate a plurality of comparison results with respect to the plurality of comparison voltages based on a sampling period; a calculation unit configured to skip a comparison result generated by a comparison voltage having a smallest difference between the analog input voltages among the plurality of comparison voltages from the plurality of comparison results, and to generate an end of comparison based on a remaining plurality of comparison results; and a SAR logic unit configured to generate a digital signal corresponding to the end of comparison and to store information for each bit of the digital signal, wherein the signal generating unit comprises: a comparison unit configured to invert a phase of at least one of the plurality of comparison voltages to generate a plurality of enlarged comparison voltages, and to output the plurality of comparison results based on the plurality of enlarged comparison voltages.

2 . The analog-to-digital conversion device of claim 1 , wherein the signal generating unit includes:
a sampling/hold circuit configured to sample the analog input voltage to a sampling voltage based on the sampling period; and a converter circuit configured to convert the sampling voltage into the plurality of comparison voltages.

3 . The analog-to-digital conversion device of claim 2 , wherein the converter circuit performs a capacitor switching operation for adjusting the sampling period of the sampling voltage.

4 . The analog-to-digital conversion device of claim 1 , wherein the analog-to-digital conversion device is configured to detect a predetermined range in the sampling period.

5 . The analog-to-digital conversion device of claim 1 , wherein the end of comparison is output as a logic high level or a logic low level.

6 . A method of operating an analog-to-digital conversion device, the method comprising:
generating a plurality of comparison voltages based on an analog input voltage, and generating a plurality of comparison results with respect to the plurality of comparison voltages based on a sampling period; skipping a comparison result generated by a comparison voltage having a smallest difference between the analog input voltages among the plurality of comparison voltages from the plurality of comparison results, and generating an end of comparison based on a remaining plurality of comparison results; and generating a digital signal corresponding to the end of comparison and storing information for each bit of the digital signal, wherein the generating of the plurality of comparison results comprises inverting a phase of at least one of the plurality of comparison voltages to generate a plurality of enlarged comparison voltages, and outputting the plurality of comparison results based on the plurality of enlarged comparison voltages.

7 . The method of claim 6 , wherein the generating of the plurality of comparison results includes:
sampling the analog input voltage to a sampling voltage based on the sampling period; and converting the sampling voltage into the plurality of comparison voltages.

8 . The method of claim 7 , wherein the converting of the sampling voltage into the plurality of comparison voltages includes:
performing a capacitor switching operation for adjusting the sampling period of the sampling voltage.

9 . The method of claim 6 , wherein the method of operating the analog-to-digital conversion device includes detecting a predetermined range in the sampling period.

10 . The method of claim 6 , wherein the end of comparison is output as a logic high level or a logic low level.

Assignees

• Univ Korea Res & Bus Found

Inventors

• Kim Chulwoo
• Park Sooho
• Choi Yohan
• Kim Chang Joo

Classifications

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/462 Primary

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/361

  having a separate comparator and reference value for each quantisation level, i.e. full flash converter type · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/403 Primary

  using switched capacitors · CPC title