Circuit comprising a current mirror circuit and method for operating a circuit

Patent metadata

Field	Value
Publication number	US-12537481-B2
Application number	US-202418409300-A
Country	US
Kind code	B2
Filing date	Jan 10, 2024
Priority date	Jan 20, 2023
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

The disclosure relates to a circuit including a current mirror circuit with a current path including a first transistor and a replica current path including a second transistor. The current path is connected to the replica current path to influence a current in the replica current path based on a reference current in the current path. The current in the replica current path may be proportional to the reference current. The circuit further includes a capacitor coupled between a gate of the second transistor and a first potential, a switch coupled between a gate of the first transistor and the gate of the second transistor to selectively disconnect the gate of the first transistor from the gate of the second transistor and from a first electrode of the capacitor. The disclosure further relates to a method for operating a circuit including a current mirror circuit.

First claim

The invention claimed is:

1 . A circuit comprising:
a current mirror circuit including a current path and a replica current path;
wherein the current path comprises a first transistor,
wherein the replica current path comprises a second transistor, and
wherein the current path is connected to the replica current path to influence a current in the replica current path based on a reference current in the current path, the current in the replica current path being proportional to the reference current,
a capacitor coupled between a gate of the second transistor of the replica current path and a first potential; a switch coupled between a gate of the first transistor of the current path and the gate of the second transistor of the replica current path;
wherein the switch is configured to selectively disconnect the gate of the first transistor from the gate of the second transistor and from a first electrode of the capacitor, and
wherein the switch is controllable to connect the gate of the first transistor to the gate of the second transistor and the first electrode of the capacitor during a first phase, and to disconnect the gate of the first transistor from the gate of the second transistor and from the first electrode of the capacitor during a second phase;
a high frequency circuit configured to generate an output signal, the high frequency circuit comprising a high frequency transmitter controlled to transmit a high frequency signal during the second phase; and a control signal generator configured to receive the output signal as a feedback signal and generate a control signal for controlling the switch based on the output signal.

2 . The circuit according to claim 1 , wherein the first phase and the second phase occur periodically.

3 . The circuit according to claim 1 ,
wherein the high frequency circuit comprises a radar device and is configured to generate and/or transmit a radar signal, wherein the high frequency circuit is configured to generate the radar signal, wherein the radar device comprises frequency modulated continuous wave (FMCW) radar device, and wherein the first phase is a flyback time between frequency ramps within a frame of the high frequency signal.

4 . The circuit according to claim 1 , wherein the first phase is between frames of the high frequency signal.

5 . The circuit according to claim 1 , wherein the first potential is at one of a supply potential or a ground potential.

6 . The circuit according to claim 1 , wherein the circuit further comprises at least one of:
a voltage-controlled oscillator, or a power amplifier.

7 . The circuit according to claim 1 , wherein the switch is controlled based on the high frequency signal.

8 . The circuit according to claim 7 , wherein a frequency of the control signal depends on a frequency of the high frequency signal.

9 . The circuit according to claim 8 , wherein the frequency of the control signal is synchronized to the high frequency signal.

10 . The circuit according to claim 1 , wherein the switch is configured to charge the capacitor during the first phase, and
wherein the circuit is configured such that the gate of the second transistor is connected to the first electrode of the capacitor during the second phase such that the gate of the second transistor is controlled by a potential of the first electrode.

11 . A method for operating a circuit, the circuit comprising a current mirror circuit with a current path comprising a first transistor and a replica current path comprising a second transistor, wherein the current path is connected to the replica current path, and wherein a capacitor is coupled between a gate of the second transistor and a first potential, the method comprising:
influencing a current in the replica current path based on a reference current in the current path, the current in the replica current path being proportional to the reference current; connecting a gate of the first transistor to the gate of the second transistor and to a first electrode of the capacitor during a first phase; selectively disconnecting the gate of the first transistor from the gate of the second transistor and from the first electrode of the capacitor during a second phase; generating an output signal, wherein the output signal is a frequency-modulated continuous-wave (FMCW) signal comprising a plurality of frames and a plurality of frequency ramps within each frame of the plurality of frames; and transmitting the output signal as a high frequency signal during the second phase based on disconnecting the gate of the first transistor from the gate of the second transistor and from the first electrode of the capacitor, wherein the high frequency signal corresponds to a frequency ramp, and wherein the first phase corresponds to a flyback time of the output signal, the flyback time being a period between two consecutive frequency ramps of the plurality of frequency ramps of a respective frame.

12 . The method according to claim 11 , further comprising:
outputting the current in the replica current path to a high frequency circuit; and influencing, based on outputting the current in the replica current path to the high frequency circuit, one or more of:
a generation of the output signal, or
transmission of the high frequency signal.

13 . The method according to claim 11 , further comprising:
charging the capacitor during the first phase, and wherein the gate of the second transistor is connected to the first electrode of the capacitor during the second phase such that the gate of the second transistor is controlled by a potential of the first electrode.

14 . The method according to claim 11 , wherein the first phase and the second phase occur periodically within a respective frame.

15 . The circuit according to claim 1 , wherein the control signal depends on a frequency of the output signal.

16 . The circuit according to claim 1 , wherein the control signal generator is configured to control the switch such that the switch is closed in a synchronized manner with a frequency of the output signal.

17 . A circuit comprising:
a current mirror circuit including a current path and a replica current path;
wherein the current path comprises a first transistor,
wherein the replica current path comprises a second transistor, and
wherein the current path is connected to the replica current path to influence a current in the replica current path based on a reference current in the current path, the current in the replica current path being proportional to the reference current,
a capacitor coupled between a gate of the second transistor of the replica current path and a first potential; a switch coupled between a gate of the first transistor of the current path and the gate of the second transistor of the replica current path;
wherein the switch is configured to selectively disconnect the gate of the first transistor from the gate of the second transistor and from a first electrode of the capacitor, and
wherein the switch is controllable to connect the gate of the first transistor to the gate of the second transistor and the first electrode of the capacitor during a first phase, and to disconnect the gate of the first transistor from the gate of the second transistor and from the first electrode of the capacitor during a second phase; and
a high frequency circuit configured to generate an output signal, the high frequency circuit comprising a high frequency transmitter controlled to transmit a high frequency signal during the second pha

Assignees

• Infineon Technologies Ag

Inventors

• Padovan Fabio
• Cherniak Dmytro
• Karman Saleh
• Grimaldi Luigi
• Boi Giovanni

Classifications

• H03B2200/0038

  including a current mirror · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03B23/00 Primary

  Generation of oscillations periodically swept over a predetermined frequency range (angle-modulating circuits in general H03C3/00) · CPC title

• H03B5/1228

  the amplifier comprising one or more field effect transistors · CPC title

• H03B5/366 Primary

  and comprising means for varying the frequency by a variable voltage or current · CPC title