Systems and methods for power module for inverter for electric vehicle

US12537442B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12537442-B2
Application numberUS-202318344347-A
CountryUS
Kind codeB2
Filing dateJun 29, 2023
Priority dateSep 28, 2022
Publication dateJan 27, 2026
Grant dateJan 27, 2026

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A system includes: an inverter configured to convert DC power to AC power, wherein the inverter includes: a power module including: a first substrate, a second substrate including a source plane and a gate plane separated from the source plane by a full trench, the source plane including a step trench, and the gate plane including an electrical connection through the second substrate to a gate input connection of the power module, a semiconductor die disposed between the first substrate and the second substrate, the step trench formed in a portion of the source plane corresponding to an edge of the semiconductor die, and the semiconductor die including a gate connected to the gate plane, and a sinter element disposed between the semiconductor die and the second substrate to connect the semiconductor die to the second substrate; a battery; and a motor.

First claim

Opening claim text (preview).

What is claimed is: 1 . A system comprising: an inverter configured to convert DC power to AC power, wherein the inverter includes: a power module including: a first substrate, a second substrate including a source plane and a gate plane separated from the source plane by a full trench, the source plane including a step trench, and the gate plane including an electrical connection through the second substrate to a gate input connection of the power module, a semiconductor die disposed between the first substrate and the second substrate, the step trench formed in a portion of the source plane corresponding to an edge of the semiconductor die, and the semiconductor die including a gate connected to the gate plane, and a sinter element disposed between the semiconductor die and the second substrate to connect the semiconductor die to the second substrate; a battery configured to supply the DC power to the inverter; and a motor configured to receive the AC power from the inverter to drive the motor. 2 . The system of claim 1 , wherein a thickness of the sinter element is in a range from approximately 25 μm to approximately 50 μm. 3 . The system of claim 2 , wherein the power module is configured to exhibit a drain to source isolation voltage of at least 1200 volts. 4 . A power module comprising: a first substrate having a first outer layer and a first inner layer; a semiconductor die coupled to a surface of the first inner layer; a second substrate having a second outer layer and a second inner layer, the semiconductor die coupled to a surface of the second inner layer; and a sinter element disposed between the semiconductor die and the second inner layer, wherein the second inner layer includes a body, the body including a source plane and a gate plane separated from the source plane by a full trench, and wherein the body includes a step trench in a portion of the body corresponding to an edge of the semiconductor die. 5 . The power module of claim 4 , wherein a thickness of the sinter element is in a range from approximately 25 μm to approximately 50 μm. 6 . The power module of claim 4 , wherein a thickness of the sinter element is approximately 25 μm. 7 . The power module of claim 4 , wherein a depth of the step trench from a surface of the sinter element attached to the second inner layer to a bottom of the step trench is in a range from approximately 50 μm to approximately 75 μm. 8 . The power module of claim 4 , wherein a depth from a surface of the semiconductor die attached to the sinter element to a bottom surface of the step trench as defined by the body of the second inner layer is in a range from approximately 75 μm to approximately 100 μm. 9 . The power module of claim 4 , wherein the step trench is in the portion of the body corresponding to the edge of the semiconductor die so that a line extending from the edge of the semiconductor die to the body, in a direction orthogonal to the surface of the second inner layer, intersects the step trench. 10 . The power module of claim 4 , wherein a width of the step trench is in a range from approximately 400 μm to approximately 500 μm. 11 . The power module of claim 4 , wherein: the full trench extends through the body to an insulating layer of the second substrate, and the step trench has a depth that is less than a thickness of the body. 12 . The power module of claim 4 , wherein the step trench is disposed in the source plane and the gate plane. 13 . The power module of claim 4 , wherein the semiconductor die includes a source connection, wherein the source connection is coupled to the source plane of the second inner layer of the second substrate. 14 . The power module of claim 4 , wherein the second substrate further includes a middle layer between the second inner layer and the second outer layer, wherein the middle layer includes a ceramic, wherein the second outer layer includes a metal, and wherein the second inner layer includes a direct bond copper metallization layer. 15 . The power module of claim 14 , wherein the step trench is in the direct bond copper metallization layer. 16 . An inverter comprising the power module of claim 4 . 17 . A vehicle comprising the inverter of claim 16 . 18 . A power module, comprising: a first substrate; a second substrate including a first trench extending through a conducting body of the second substrate to an insulating body of the second substrate, and the second substrate including a second trench extending from a surface of the second substrate into the conducting body of the second substrate at a depth less than a thickness of the conducting body; a semiconductor die disposed between the first substrate and the second substrate, the semiconductor die having a drain connection coupled to the first substrate and a source connection coupled to the second substrate; and a sinter element disposed between the semiconductor die and the second substrate, the sinter element having a thickness in a range of 25 μm to 50 μm; wherein the surface of the second substrate is attached to the sinter element. 19 . The power module of claim 18 , wherein the second trench is etched into the conducting body of the second substrate in a portion of the second substrate corresponding to an edge of the semiconductor die. 20 . The power module of claim 18 , wherein a width of the second trench is in a range of 400 μm to 500 μm.

Assignees

Inventors

Classifications

  • Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

  • Transistor · CPC title

  • Stacked spaced PCBs; Planar parts of folded flexible circuits having mounted components in between or spaced from each other · CPC title

  • characterised by the heat transfer by conduction from the heat generating element to a dissipating body (arrangements for increasing/decreasing heat-transfer, e.g. fins details, F28F13/00) · CPC title

  • Electrical details of casings, e.g. terminals, passages for cables or wiring · CPC title

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What does patent US12537442B2 cover?
A system includes: an inverter configured to convert DC power to AC power, wherein the inverter includes: a power module including: a first substrate, a second substrate including a source plane and a gate plane separated from the source plane by a full trench, the source plane including a step trench, and the gate plane including an electrical connection through the second substrate to a gate …
Who is the assignee on this patent?
Borgwarner Us Tech Llc
What technology area does this patent fall under?
Primary CPC classification H02M1/327. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 27 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).