Device, system and method to deliver power with phase circuits of an integrated circuit die

Patent metadata

Field	Value
Publication number	US-12537433-B2
Application number	US-202217851997-A
Country	US
Kind code	B2
Filing date	Jun 28, 2022
Priority date	Jun 28, 2022
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

Techniques and mechanisms for facilitating a scalable delivery of current to an inductor of a voltage regulator. In an embodiment, a hardware interface of integrated circuit (IC) die accommodates coupling of the IC die to multiple inductors. The hardware interface comprises contacts which are each to couple the IC die to a respective one of the multiple inductors. A phase circuit of the IC die includes multiple cells which are each coupled to a different respective contact of a plurality of contacts of the hardware interface. A digital controller of the IC die is operable to select any of various combinations of the multiple cells each to conduct a respective current with a corresponding one of the plurality of contacts. In another embodiment, the plurality of contacts are arranged as a multi-row, multi-column array.

First claim

What is claimed is:

1 . An integrated circuit (IC) die comprising:
a hardware interface comprising first conductive contacts which are each to couple the IC die to a first inductor; a digital controller to generate a first one or more driver signals; and a first phase circuit comprising a first plurality of cells each comprising:
a bridge circuit; and
a switch circuit;

wherein, for each of the first plurality of cells, the digital controller is to indicate, to the switch circuit, whether to provide a respective one or more conductive paths to enable the cell to conduct a current with a corresponding one of the first conductive contacts, wherein the current is to be generated with the bridge circuit based on the first one or more driver signals;
wherein the first plurality of cells are each coupled to a different one of the first conductive contacts, and wherein the first conductive contacts are arranged relative to each other as a first array which comprises first rows and first columns.

2 . The IC die of claim 1 , wherein the first plurality of cells are arranged relative to each other as a second array which comprises second rows and second columns.

3 . The IC die of claim 1 , wherein the first phase circuit is one of multiple phase circuits of the IC die, wherein the multiple phase circuits each comprise a respective plurality of cells each comprising a respective bridge circuit and a respective switch circuit, wherein the multiple phase circuits comprise:
a first plurality of phase circuits which are each in a first region; and a second plurality of phase circuits which are each in a second region;
wherein the first region and the second region extend on opposite respective sides of the digital controller.

4 . The IC die of claim 1 , wherein the first phase circuit comprises a first cell which is coupled to a first conductive contact of the first plurality of conductive contacts, wherein the first cell comprises a first bridge circuit and a first switch circuit, wherein the first switch circuit is operable to selectively provide or prevent a conductive path between an output of the first bridge circuit and the first conductive contact.

5 . The IC die of claim 1 , wherein the first phase circuit comprises a first cell which is coupled to a first conductive contact of the first plurality of conductive contacts, wherein the first cell comprises a first bridge circuit and a first switch circuit, wherein the first switch circuit is operable to selectively provide or prevent a conductive path between an input of the first bridge circuit and the digital controller.

6 . The IC die of claim 1 , wherein the first phase circuit is one of multiple phase circuits of the IC die, wherein the multiple phase circuits each comprise a respective plurality of cells each comprising a respective bridge circuit and a respective switch circuit, wherein the digital controller comprises a pulse width modulator, the IC die further comprising:
a plurality of current balance circuits each corresponding to a different respective two or more phase circuits of the multiple phase circuits, wherein:
the plurality of current balance circuits are coupled to each other to generate a first indication of a first total amount of current output by multiple phase circuits comprising the plurality of phase circuits;
for each current balance circuit of the plurality of current balance circuits:
the current balance circuit is further coupled to receive a respective second indication of a respective second total amount of current output by the corresponding two or more phase circuits;
the current balance circuit is to generate, based on the first indication and the respective second indication, a respective signal which indicates an adjustment to be made to a respective signal from the pulse width modulator.

7 . The IC die of claim 6 , wherein, for each current balance circuit of the plurality of current balance circuits, the current balance circuit is to generate the respective signal based on a difference between the first indication to the respective second indication.

8 . The IC die of claim 6 , wherein:
the hardware interface comprises multiple conductive contacts each to couple the IC die to a respective one of a plurality of inductors; a first voltage regulator is to comprise the plurality of inductors, the digital controller, the plurality of phase circuits, and the plurality of current balance circuits; the digital controller is a first digital controller which comprises:
a first pulse width modulator; and
a first compensator circuit coupled to the first pulse width modulator, wherein the first compensator circuit to further couple to a second digital controller of a second voltage regulator;
the second digital controller is to generate a pulse width modulated signal; the first compensator circuit is further to generate a compensation signal to indicate, to the second digital controller, a duty cycle to be provided with the pulse width modulated signal.

9 . The IC die of claim 8 , wherein:
the plurality of phase circuits is a first plurality of phase circuits; the plurality of current balance circuits is a first plurality of current balance circuits; the second voltage regulator is to further comprise:
a second plurality of phase circuits; and
a second plurality of current balance circuits each corresponding to a different respective two or more phase circuits of the second plurality of phase circuits;
the first plurality of current balance circuits are further to couple to the second plurality of current balance, wherein the multiple phase circuits are to further comprise the second plurality of phase circuits; the first plurality of phase circuits is to generate the first indication with the second plurality of phase circuits.

10 . An integrated circuit (IC) die comprising:
a hardware interface comprising multiple contacts; phase circuits which each correspond to a different respective plurality of contacts of the hardware interface, the phase circuits each comprising a respective plurality of cells, wherein, for each of the phase circuits, the respective plurality of cells of the phase circuit are each coupled to a different respective contact of the corresponding plurality of contacts, wherein the corresponding plurality of contacts are arranged relative to each other as an array which comprises multiple rows and multiple columns; and a digital controller coupled to the phase circuits, wherein, for each phase circuit of one or more of the phase circuits, the digital controller is to:
provide a respective pair of driver signals to the phase circuit; and
select a respective one or more cells of the phase circuit each to output a respective current based on the respective pair of driver signals;

wherein the phase circuits comprise a first plurality of phase circuits which are each in a first region, and a second plurality of phase circuits which are each in a second region, wherein the first region and the second region extend on opposite respective sides of the digital controller.

11 . The IC die of claim 10 , wherein, for each of the phase circuits, the respective plurality of cells of the phase circuit are arranged relative to each other as a cell array which comprises multiple cell rows and multiple cell columns.

12 . The IC die of claim 10 , wherein, for each of the phase circuits, the plurality of cells of the phase circuit each comprising a respective bridge circuit and a respective switch circuit, wherein the phase circuits comprise:
a first plurality of phase circuits which are each in a first region; a

Assignees

• Intel Corp

Inventors

• Salus Tamir
• Xu Shunjiang
• Schaef Christopher

Classifications

• H02M3/155

  using semiconductor devices only · CPC title

• H02M1/088

  for the simultaneous control of series or parallel connected semiconductor devices · CPC title

• H02M1/0012

  Control circuits using digital or numerical techniques (in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873) · CPC title

• H02M1/0043 Primary

  Converters switched with a phase shift, i.e. interleaved (non-isolated DC/DC converters H02M3/1586) · CPC title

• H02M3/157

  with digital control · CPC title