Technologies for on-memory die voltage regulator

Patent metadata

Field	Value
Publication number	US-12361979-B2
Application number	US-202117482353-A
Country	US
Kind code	B2
Filing date	Sep 22, 2021
Priority date	Sep 22, 2021
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

Techniques for an on-memory die voltage regulator is disclosed. In the illustrative embodiment, a voltage regulator on a memory die is enabled upon receipt of a memory operation. The illustrative voltage regulator includes an analog controller that controls a shunt current based on a current output voltage of the voltage regulator. The illustrative voltage regulator also includes a digital controller that controls several switches based on the input voltage that control an effective resistance of part of the voltage regulator.

First claim

The invention claimed is:

1. A memory die comprising:
a voltage regulator; and
controller circuitry to activate the voltage regulator in response to receipt of a memory operation, wherein the controller circuitry is to activate the voltage regulator in response to receipt of a memory write operation.

2. The memory die of claim 1 , wherein the voltage regulator is a linear voltage regulator.

3. The memory die of claim 2 , wherein a dropout of the voltage regulator is less than 100 millivolts.

4. The memory die of claim 1 , further comprising digital controller circuitry to control a digital state of one or more transistors based on an input voltage of the voltage regulator.

5. The memory die of claim 4 , further comprising analog controller circuitry to control a shunt current through a transistor based on an output voltage of the voltage regulator.

6. The memory die of claim 5 , wherein the analog controller circuitry is to control the shunt current through the transistor based on an efficiency parameter of the voltage regulator.

7. The memory die of claim 5 , wherein the analog controller circuitry comprises an operational amplifier, wherein the digital controller circuitry comprises a plurality of comparators.

8. The memory die of claim 7 , wherein the digital controller circuitry comprises a plurality of different reference voltages, wherein each of the plurality of different references voltages is connected to a first input of different comparator of the plurality of comparators,
wherein the input voltage of the voltage regulator is connected to a second input of each of the plurality of comparators.

9. The memory die of claim 7 , wherein an output voltage of the voltage regulator is connected to a first input of the operational amplifier,
wherein a target output voltage is connected to a second input of the operational amplifier,
wherein an output of the operational amplifier is connected to a gate of the transistor,
wherein a source of the transistor is connected to the output voltage of the voltage regulator,
wherein a drain of the transistor is connected to a ground.

10. The memory die of claim 1 , wherein the controller circuitry is not to activate the voltage regulator in response to receipt of a memory read operation.

11. The memory die of claim 1 , wherein the voltage regulator has a settling time of less than one nanosecond.

12. An integrated circuit component comprising:
a linear voltage regulator comprising:
analog controller circuitry to control a shunt current through a transistor based on an output voltage of the linear voltage regulator, and
digital controller circuitry to control a digital state of one or more transistors based on an input voltage of the linear voltage regulator,

wherein the digital controller circuitry comprises a plurality of comparators,
wherein the digital controller circuitry comprises a plurality of different reference voltages, wherein individual reference voltages of the plurality of different references voltages is connected to a first input of different comparator of the plurality of comparators,
wherein the input voltage of the linear voltage regulator is connected to a second input of individual comparators of the plurality of comparators.

13. The integrated circuit component of claim 12 , wherein the analog controller circuitry comprises an operational amplifier.

14. The integrated circuit component of claim 13 , wherein the output voltage of the linear voltage regulator is connected to a first input of the operational amplifier,
wherein a target output voltage is connected to a second input of the operational amplifier,
wherein an output of the operational amplifier is connected to a gate of the transistor,
wherein a source of the transistor is connected to the output voltage of the linear voltage regulator,
wherein a drain of the transistor is connected to a ground.

15. The integrated circuit component of claim 12 , wherein the integrated circuit component is a memory die.

16. A memory die comprising:
a linear voltage regulator comprising:
analog controller circuitry to control a shunt current through a transistor based on an output voltage of the linear voltage regulator; and
digital controller circuitry to control a digital state of one or more transistors based on an input voltage of the linear voltage regulator,
wherein the analog controller circuitry and the digital controller circuitry generate a regulated voltage with a settling time of less than 1 nanosecond; and
wherein the analog controller circuitry and the digital controller circuitry generate the regulated voltage with a variation of less than 100 millivolts.

17. The memory die of claim 16 , wherein the linear voltage regulator comprises circuitry for generating the regulated voltage at an efficiency of at least 70%.

18. The memory die of claim 16 , further comprising circuitry for controlling an efficiency of the linear voltage regulator.

19. The memory die of claim 16 , wherein the digital controller circuitry comprises a plurality of comparators,
wherein the digital controller circuitry comprises a plurality of different reference voltages, wherein individual reference voltages of the plurality of different references voltages is connected to a first input of different comparator of the plurality of comparators,
wherein the input voltage of the linear voltage regulator is connected to a second input of individual comparators of the plurality of comparators.

20. The memory die of claim 16 , wherein the analog controller circuitry comprises an operational amplifier.

Assignees

• Intel Corp

Inventors

• Garag Veeresh
• Chauhan Bharat V

Classifications

• G05F1/562 Primary

  with a threshold detection shunting the control path of the final control device · CPC title

• G06F1/28

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C13/0038

  Power supply circuits · CPC title