Memory device

Patent metadata

Field	Value
Publication number	US-12537070-B2
Application number	US-202118026654-A
Country	US
Kind code	B2
Filing date	Sep 8, 2021
Priority date	Sep 22, 2020
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

A highly reliable memory device is provided. The memory device includes a memory control unit that includes an input/output unit, a control unit, and a first management unit and a memory unit that includes a plurality of memory blocks. The first management unit includes a plurality of first memory elements, the control unit has a function of converting an address input through the input/output unit to an address of the memory block corresponding to the address, with use of a first management table retained in the plurality of first memory elements, and the first memory elements each include a ferroelectric. The control portion may include a function of not using a defective memory cell and may have a function of performing error correction of readout data.

First claim

The invention claimed is:

1 . A memory device comprising:
a memory control unit comprising an input/output unit, a control unit, and a first management unit; and a memory unit comprising a plurality of memory blocks, wherein the first management unit comprises a plurality of first memory elements, wherein the control unit is configured to convert an address input through the input/output unit to an address of the memory block corresponding to the address, with use of a first management table retained in the plurality of first memory elements, and wherein each of the plurality of first memory elements comprises a first transistor, a second transistor, and a first capacitor, wherein the first capacitor comprises a ferroelectric layer, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and to one electrode of the first capacitor, and wherein the first transistor has a back gate, and the second transistor does not have a back gate.

2 . The memory device according to claim 1 ,
wherein the memory control unit comprises a second management unit, wherein the second management unit comprises a plurality of second memory elements, wherein the control unit is configured to select a memory block in which data can be written, from the plurality of memory blocks, with use of a second management table retained in the plurality of second memory elements, and wherein each of the plurality of second memory elements comprises a ferroelectric.

3 . The memory device according to claim 1 ,
wherein the memory control unit comprises a third management unit, wherein the third management unit comprises a plurality of third memory elements, wherein the control unit is configured to determine whether error correction is necessary or not at the time of reading out data, with use of a third management table retained in the plurality of third memory elements, and wherein each of the plurality of third memory elements comprises a ferroelectric.

4 . The memory device according to claim 1 ,
wherein each of the plurality of memory blocks comprises a plurality of memory elements, and wherein each of the plurality of memory elements is a NAND-type memory element.

5 . The memory device according to claim 1 ,
wherein the ferroelectric comprises one or both of hafnium and zirconium.

6 . The memory device according to claim 1 ,
wherein a concentration of hydrogen in the ferroelectric is 5×10 20 atoms/cm 3 or lower.

7 . The memory device according to claim 1 ,
wherein a concentration of carbon in the ferroelectric is 5×10 19 atoms/cm 3 or lower.

Assignees

• Semiconductor Energy Lab

Inventors

• Matsuzaki Takanori
• Onuki tatsuya
• Aoki Takeshi

Classifications

• G06F2212/2022

  Flash memory · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G11C29/44 Primary

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/883

  using a single defective memory device with reduced capacity, e.g. half capacity · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title