Manufacturing method of a nonvolatile semiconductor memory device

Patent metadata

Field	Value
Publication number	US-11362106-B2
Application number	US-202117141504-A
Country	US
Kind code	B2
Filing date	Jan 5, 2021
Priority date	Mar 27, 2006
Publication date	Jun 14, 2022
Grant date	Jun 14, 2022

Abstract

A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

First claim

What is claimed is:

1. A manufacturing method of a nonvolatile semiconductor memory device comprising:
forming first films and second films alternately in a first direction perpendicular to a surface of a semiconductor substrate, a material of the first films being different from a material of the second films;
forming holes in the first films and the second films, the holes extending in the first direction, the holes including a first hole, a second hole and a third hole, the first hole and the second hole being arranged in a second direction perpendicular to the first direction, the first hole and the third hole being arranged in a third direction perpendicular to the first direction and the second direction;
forming a first insulating film in the holes;
forming a semiconductor film in the holes after forming the first insulating film; and
dividing the first films and second films into a first unit and a second unit in the second direction after forming the semiconductor film, the first hole, the second hole and the third hole being in the first unit.

2. The manufacturing method according to claim 1 , further comprising:
etching a lower end of the first insulating film.

3. The manufacturing method according to claim 1 , further comprising:
forming a stepwise-shaped structure at an end portion of the first films in the third direction.

4. The manufacturing method according to claim 1 , further comprising:
forming a stepwise-shaped structure at an end portion of the first films in the third direction before forming the holes.

5. The manufacturing method according to claim 1 , further comprising:
dividing an uppermost film of the first films into a first upper film and a second upper film in the second direction.

6. The manufacturing method according to claim 5 , wherein the first hole and the third hole are in the first upper film, and the second hole is in the second upper film.

7. The manufacturing method according to claim 1 , further comprising:
forming a semiconductor portion in one of the holes before forming the insulating film, the upper surface of the semiconductor portion being above an upper surface of a lowermost film of the first films,
wherein a lower end of the first insulating film is positioned on the semiconductor portion in forming the insulating film.

8. The manufacturing method according to claim 1 , wherein the first insulating film includes a block insulating film, a charge trap film and a tunnel insulating film.

9. The manufacturing method according to claim 8 , wherein the charge trap film is silicon nitride.

10. The manufacturing method according to claim 1 , wherein the second films are silicon oxide.

11. A manufacturing method of a nonvolatile semiconductor memory device comprising:
forming first films and second films alternately in a first direction perpendicular to a surface of a semiconductor substrate, a material of the first films being different from a material of the second films, the first films including an upper film and a lower film;
forming holes in the first films and the second films, the holes extending in the first direction, the holes including a first hole, a second hole and a third hole, the first hole and the second hole being arranged in a second direction perpendicular to the first direction, the first hole and the third hole being arranged in a third direction perpendicular to the first direction and the second direction;
forming a first insulating film in the holes;
forming a semiconductor film in the holes after forming the first insulating film; and
forming a first trench extending in the third direction, the first trench dividing the upper film into a first upper film and a second upper film in the second direction, a lower end of the first trench being above the lower film.

12. The manufacturing method according to claim 11 , wherein the first hole and the third hole are in the first upper film, and the second hole is in the second upper film.

13. The manufacturing method according to claim 11 , further comprising:
etching a lower end of the first insulating film.

14. The manufacturing method according to claim 11 , further comprising:
forming a stepwise-shaped structure at an end portion of the first films in the third direction.

15. The manufacturing method according to claim 11 , further comprising:
forming a stepwise-shaped structure at an end portion of the first films in the third direction before forming the holes.

16. The manufacturing method according to claim 11 , further comprising:
forming a second trench extending in the third direction, the second trench dividing the first films and the second films into a first unit and a second unit in the second direction, a lower end of the second trench being below the lower film, wherein the first hole, the second hole and the third hole are in the first unit.

17. The manufacturing method according to claim 16 , wherein forming the second trench is after forming the semiconductor film.

18. The manufacturing method according to claim 11 , further comprising:
forming a semiconductor portion in one of the holes before forming the insulating film, the upper surface of the semiconductor portion being above an upper surface of a lowermost film of the first films,
wherein a lower end of the first insulating film is positioned on the semiconductor portion in forming the insulating film.

19. The manufacturing method according to claim 11 , wherein the first insulating film includes a block insulating film, a charge trap film and a tunnel insulating film.

20. The manufacturing method according to claim 11 , wherein the second films are silicon oxide.

Assignees

• Kioxia Corp

Inventors

• Kito Masaru
• Aochi Hideaki
• Katsumata Ryota
• Nitayama Akihiro
• Kidoh Masaru
• Tanaka Hiroyasu
• Fukuzumi Yoshiaki
• Matsuoka Yasuyuki
• Sato Mitsuru

Classifications

• H10D84/038 Primary

  using silicon technology, e.g. SiGe · CPC title

• H10D88/01

  Manufacture or treatment · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H01L27/11578

  Electricity · mapped topic