System, method and apparatus for high level microarchitecture event performance monitoring using fixed counters

Patent metadata

Field	Value
Publication number	US-12536086-B2
Application number	US-202117556751-A
Country	US
Kind code	B2
Filing date	Dec 20, 2021
Priority date	Dec 20, 2021
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

In one embodiment, an apparatus includes: at least one core to execute instructions; and a plurality of fixed counters coupled to the at least one core, the plurality of fixed counters to count events during execution on the at least one core, at least some of the plurality of fixed counters to count event information of a highest level of a hierarchical performance monitoring organization. Other embodiments are described and claimed.

First claim

What is claimed is:

1 . An apparatus comprising:
at least one processor core to execute instructions; and a plurality of fixed counters coupled to the at least one processor core, the plurality of fixed counters to count performance monitoring events during execution of the instructions on the at least one processor core, at least some of the plurality of fixed counters to count performance monitoring events associated with a highest level of a hierarchical performance monitoring organization, the counted performance monitoring events associated with the highest level of the hierarchical performance monitoring organization being usable to monitor execution performance of a workload including the instructions.

2 . The apparatus of claim 1 , wherein a first fixed counter of the plurality of fixed counters is configured to count first events associated with a front end bound condition.

3 . The apparatus of claim 2 , wherein a second fixed counter of the plurality of fixed counters is configured to count second events associated with a back end bound condition.

4 . The apparatus of claim 3 , wherein a third fixed counter of the plurality of fixed counters is configured to count misspeculation events.

5 . The apparatus of claim 4 , wherein a fourth fixed counter of the plurality of fixed counters is configured to count retirement events.

6 . The apparatus of claim 2 , further comprising a configuration register to store configuration information, wherein the configuration register comprises a first field to store a first indicator, when set, to enable the first fixed counter to count the first events.

7 . The apparatus of claim 2 , wherein the first fixed counter is to count a raw number of the first events.

8 . The apparatus of claim 7 , further comprising a computation circuit to determine a percentage of slots during which the first events occur, based at least in part on the raw number of the first events.

9 . The apparatus of claim 1 , further comprising a plurality of programmable counters.

10 . The apparatus of claim 9 , further comprising a performance monitoring unit coupled to the at least one processor core, wherein the performance monitoring unit comprises the plurality of fixed counters and the plurality of programmable counters.

11 . A method comprising:
executing instructions by at least one processor core; and during execution of the instructions by the at least one processor core, counting first events of a highest hierarchical level of a performance monitoring organization by updating a first fixed counter of a plurality of fixed counters coupled to the at least one processor core, the counted first events being usable to monitor execution performance of a workload including the instructions.

12 . The method of claim 11 , further comprising enabling, via a control circuit, the first fixed counter to maintain the count of first events.

13 . The method of claim 11 , further comprising reading a value of the first fixed counter and storing the value into a storage, the value comprising a raw count of first events occurring during execution of the workload.

14 . The method of claim 11 , further comprising enabling the first fixed counter to maintain the count of first events associated with a front end bound condition.

15 . The method of claim 12 , further comprising enabling, via the control circuit, a second fixed counter to maintain a count of second events, the second events of the highest hierarchical level of the performance monitoring organization.

16 . The method of claim 11 , further comprising determining a percentage of slots during which the first events occur based at least in part on the count of first events, wherein determining the percentage of slots comprises calculating the percentage of slots using the count of first events and a count of slots obtained from another fixed counter of the plurality of fixed counters.

17 . The method of claim 12 , wherein enabling the first fixed counter comprises setting an indicator in a field of at least one configuration register, the field associated with the first fixed counter.

18 . A system comprising:
a processor comprising:
at least one processor core to execute instructions, and
a plurality of fixed counters coupled to the at least one processor core, the plurality of fixed counters the plurality of fixed counters to count performance monitoring events during execution of the instructions on the at least one processor core, at least some of the plurality of fixed counters to count performance monitoring events associated with a highest level of a hierarchical performance monitoring organization, the counted performance monitoring events associated with the highest level of the hierarchical performance monitoring organization being usable to monitor execution performance of a workload including the instructions; and
a memory coupled to the processor.

19 . The system of claim 18 wherein the at least one processor core comprises:
front end circuitry to fetch and decode instructions;
back end circuitry to execute and retire the instructions;
at least one configuration register to store configuration information; and
performance monitoring circuitry coupled to the front end circuitry and the back end circuitry, the performance monitoring circuitry comprising:
the plurality of fixed counters,
a plurality of programmable counters, wherein the programmable counters are programmable to count events of one or more levels of the hierarchical performance monitoring organization lower than the highest level, and
a control circuit to enable one or more of the plurality of fixed counters and one or more of the plurality of programmable counters, in response to at least one write to the at least one configuration register.

20 . The system of claim 19 , wherein the plurality of fixed counters comprises:
a first fixed counter to count events associated with a bound condition of the front end circuitry; a second fixed counter to count events associated with a bound condition of the back end circuitry; a third fixed counter to count misspeculation events; and a fourth fixed counter to count retirement events.

Assignees

• Intel Corp

Inventors

• Romo Claudia
• Combs Jonathan
• Strong Beeman

Classifications

• G06F11/3409 Primary

  for performance assessment · CPC title

• G06F11/3072

  where the reporting involves data filtering, e.g. pattern matching, time or event triggered, adaptive or policy-based reporting · CPC title

• G06F9/30101

  Special purpose registers · CPC title

• G06F11/3466 Primary

  Performance evaluation by tracing or monitoring · CPC title

• G06F2201/86

  Event-based monitoring · CPC title