Wafer scale active thermal interposer for device testing

Patent metadata

Field	Value
Publication number	US-12535522-B2
Application number	US-202519201257-A
Country	US
Kind code	B2
Filing date	May 7, 2025
Priority date	Nov 19, 2020
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

An apparatus for use in testing an integrated circuit semiconductor wafer device under test (wafer DUT) includes a probe configured to probe a surface of the wafer DUT during testing thereof, a thermal interposer (TI) including a heater layer arranged with a plurality of zones corresponding to a plurality of areas of the wafer DUT, the TI configured to come into proximity to a surface of the wafer DUT and further configured to selectively heat the plurality of areas by selectively heating the plurality of zones, the heater layer including a plurality of heating elements configured to correspond to the plurality of zones, and a plurality of temperature measurement devices configured to correspond to the plurality of zones, a cold plate disposed in proximity to the TI and configured to selectively cool the plurality of areas of the wafer DUT, and a thermal controller configured to control selective cooling of the cold plate and configured to control selective heating of the plurality of heating elements of the TI during the testing.

First claim

What is claimed is:

1 . An apparatus for use in testing an integrated circuit semiconductor wafer device under test (wafer DUT), the apparatus comprising:
a probe configured to probe a surface of said wafer DUT during testing thereof; a thermal interposer (TI) comprising a top surface and a bottom surface, and further comprising a heater layer arranged with a plurality of zones corresponding to a plurality of areas of said wafer DUT, said TI configured to come into proximity to a surface of said wafer DUT and further configured to selectively heat said plurality of areas by selectively heating said plurality of zones, said heater layer comprising:
a plurality of heating elements configured to correspond to said plurality of zones; and
a plurality of temperature measurement devices configured to correspond to said plurality of zones;
a cold plate disposed in proximity to said TI and configured to selectively cool said plurality of areas of said wafer DUT; and a thermal controller configured to control selective cooling of said cold plate and configured to control selective heating of said plurality of heating elements of said TI during said testing.

2 . The apparatus as described in claim 1 wherein said thermal controller is responsive to measurements from said plurality of temperature measurement devices and wherein further said plurality of temperature measurement devices are interposed within said plurality of heating elements.

3 . The apparatus as described in claim 2 wherein said plurality of temperature measurement devices comprises a plurality of resistance temperature devices (RTDs).

4 . The apparatus as described in claim 2 wherein said plurality of heating elements of said TI comprise a plurality of resistive traces.

5 . The apparatus as described in claim 1 wherein said plurality of temperature measurement devices comprises a plurality of diodes.

6 . The apparatus as described in claim 1 wherein said plurality of temperature measurement devices comprises a plurality of thermocouples.

7 . The apparatus as described in claim 1 wherein positions of said plurality of zones of said TI correspond to and are customized for a die layout of said wafer DUT.

8 . The apparatus as described in claim 1 wherein said TI further comprises:
an electromagnetic interference (EMI) shield layer comprising said top surface and disposed to shield said top surface from EMI of said heater layer and wherein said shield layer is configured to be grounded.

9 . The apparatus as described in claim 1 wherein said TI further comprises vacuum channels configured secure said wafer DUT in place with respect to said TI by holding a vacuum there between.

10 . The apparatus as described in claim 1 wherein said TI further comprises:
a first thermal interface material (TIM) layer disposed between said cold plate and said bottom surface of said TI; and
a second thermal interface material (TIM) layer disposed on said top surface of said TI.

11 . The apparatus as described in claim 10 wherein said first and second TIM layers comprise a polymer film.

12 . The apparatus as described in claim 10 wherein said first and second TIM layers comprise water.

13 . The apparatus as described in claim 1 wherein each zone of said plurality of zones of said TI corresponds to a respective single die of a die layout of said wafer DUT.

14 . The apparatus as described in claim 1 wherein each zone of said plurality of zones of said TI corresponds to a respective plurality of dice of a die layout of said wafer DUT.

15 . The apparatus as described in claim 1 wherein each die of a die layout of said wafer DUT corresponds to multiple respective zones of said plurality of zones of said TI.

16 . The apparatus as described in claim 1 wherein a shape of said TI is generally circular and wherein said plurality of heating elements is arranged in an orthogonal array or in a polar or radial fashion.

17 . The apparatus as described in claim 1 further comprising:
a chiller for cooling liquid; and
a valve for controlling an amount of said liquid flowing to said cold plate, wherein said valve is controlled by said thermal controller.

18 . The apparatus as described in claim 1 further comprising a power supply controlled by said thermal controller, said power supply configured to selectively provide power to said plurality of heating elements based on pulse width modulated (PWM) voltage signals.

19 . The apparatus as described in claim 1 wherein said plurality of heating elements comprises a dielectric layer comprising: aluminum nitride (AlN); and a plurality of conductive traces disposed on said dielectric layer.

20 . A method of temperature regulation of an integrated circuit semiconductor wafer device under test (DUT) during testing thereof, the method comprising:
probing said wafer DUT during said testing using a wafer probe; and in conjunction with said testing, selectively heating a plurality of areas of said wafer DUT using a thermal controller controlling a thermal interposer, wherein said thermal interposer comprises a top surface and a bottom surface, disposed in proximity to said wafer DUT, to selectively heat a plurality of separately controllable thermal zones arranged in a heater layer of said thermal interposer, wherein said thermal controller is responsive to temperature measurements from a plurality of temperature measurement devices comprised in said heater layer; and in conjunction with said testing, selectively cooling said plurality of areas of said wafer DUT using said thermal controller controlling a cold plate, said cold plate disposed in proximity to said wafer DUT.

21 . The method as described in claim 20 wherein said heater layer further comprises a plurality of resistive elements arranged to form said plurality of separately controllable thermal zones and wherein further said selectively heating said plurality of separately controllable thermal zones comprises:
said thermal controller reading said temperature measurements from said plurality of temperature measurement devices; and
responsive to said temperature measurements, said thermal controller controlling selective energizing of said plurality of resistive elements.

22 . The method as described in claim 21 wherein said thermal interposer further comprises an electromagnetic interference (EMI) shield layer disposed between said plurality of resistive elements and said wafer DUT and wherein further said selectively cooling said plurality of areas of said wafer DUT using said thermal controller controlling said cold plate comprises said thermal controller controlling selective cooling of said cold plate responsive to said temperature measurements.

23 . The method as described in claim 21 wherein a shape of said thermal interposer is generally circular and wherein said plurality of resistive elements is arranged in an orthogonal array or in a polar or radial fashion.

24 . The method as described in claim 21 further comprising a power supply and wherein said thermal controller controlling the selective energizing of said plurality of resistive elements comprises said thermal controller causing said power supply to selectively provide power to said plurality of resistive elements based on modulated voltage signals from said power supply and wherein said modulated voltage signals are pulse width modulated (PWM) voltage signals.

Assignees

• Advantest Test Solutions Inc

Inventors

• Kabbani Samer
• Ferrari Paul
• Hiroki Ikeda
• Toshiyuki Kiyokawa
• Cruzan Gregory
• Ranganathan Karthik

Classifications

• F28F2260/02

  having microchannels · CPC title

• H01L23/473

  Electricity · mapped topic

• G01R31/318511

  Wafer Test · CPC title

• G01R31/2887 Primary

  involving moving the probe head or the IC under test; docking stations (moving single probes G01R1/06705; moving individual probes in multiple probes G01R1/07392) · CPC title

• H10W40/47

  by flowing liquids, e.g. forced water cooling · CPC title