MIM capacitor and fabricating method of the same

Patent metadata

Field	Value
Publication number	US-12532485-B2
Application number	US-202318233899-A
Country	US
Kind code	B2
Filing date	Aug 15, 2023
Priority date	Jul 24, 2023
Publication date	Jan 20, 2026
Grant date	Jan 20, 2026

Abstract

A metal-insulator-metal capacitor includes a bottom electrode, a dielectric layer, a superlattice layer, a silicon dioxide layer and a top electrode stacked from bottom to top. The superlattice layer contacts the dielectric layer. A silicon dioxide layer has a negative voltage coefficient of capacitance.

First claim

What is claimed is:

1 . A metal-insulator-metal (MIM) capacitor, comprising:
a bottom electrode, a dielectric layer, a superlattice layer, a silicon dioxide layer and a top electrode stacked from bottom to top; wherein the superlattice layer contacts the dielectric layer and the silicon dioxide layer, and the silicon dioxide layer has a negative voltage coefficient of capacitance, and wherein the dielectric layer comprises AlN x or BN x .

2 . The MIM capacitor of claim 1 , wherein the silicon dioxide layer is annealed and polarized silicon dioxide.

3 . The MIM capacitor of claim 1 , wherein the silicon dioxide layer is amorphous silicon dioxide.

4 . The MIM capacitor of claim 1 , wherein the superlattice layer comprises perovskite material layers not less than 5 layers.

5 . The MIM capacitor of claim 1 , wherein the superlattice layer comprises perovskite material layers not less than 5 layers, and a thickness of each of the perovskite material layers is between 10 nm and 60 nm.

6 . The MIM capacitor of claim 1 , wherein the superlattice layer comprises SrTiO x , BaTiO x , CaTiO x , CaMgO x or PbTiO x .

7 . The MIM capacitor of claim 1 , wherein the superlattice layer has a positive voltage coefficient of capacitance.

8 . The MIM capacitor of claim 1 , wherein the top electrode comprises TiN, Al, Ta, Cu, Ti or Ta, and the bottom electrode comprises TiN, Al, Ta, Cu, Ti or Ta.

9 . The MIM capacitor of claim 1 , wherein the top electrode contacts the silicon dioxide layer, and the bottom electrode contacts the dielectric layer.

10 . A fabricating method of a metal-insulator-metal (MIM) capacitor, comprising:
forming a bottom electrode, a dielectric layer, a superlattice layer, a silicon dioxide layer and a top electrode stacked from bottom to top; wherein the superlattice layer contacts the dielectric layer and the silicon dioxide layer, and the silicon dioxide layer has a negative voltage coefficient of capacitance, and wherein the dielectric layer comprises AlN x or BN x .

11 . The fabricating method of an MIM capacitor of claim 10 , wherein steps of fabricating the superlattice layer comprise using a deposition process, periodically and alternately stacking a perovskite material layer at an operation temperature between 350 degrees Celsius to 450 degrees Celsius.

12 . The fabricating method of an MIM capacitor of claim 11 , wherein the deposition process comprises an atomic layer deposition, a chemical vapor deposition or a physical vapor deposition.

13 . The fabricating method of an MIM capacitor of claim 10 , wherein steps of fabricating the silicon dioxide layer comprise:
depositing the silicon dioxide layer; and performing an annealing process to the silicon dioxide layer at a temperature of 400 degrees Celsius.

14 . The fabricating method of an MIM capacitor of claim 10 , wherein the silicon dioxide layer is amorphous and polarized silicon dioxide.

15 . The fabricating method of an MIM capacitor of claim 10 , wherein the superlattice layer comprises perovskite material layers not less than 5 layers.

16 . The fabricating method of an MIM capacitor of claim 10 , wherein the superlattice layer comprises perovskite material layers not less than 5 layers, and a thickness of each of the perovskite material layers is between 10 nm and 60 nm.

17 . The fabricating method of an MIM capacitor of claim 10 , wherein the superlattice layer comprises SrTiO x , BaTiO x , CaTiO x , CaMgO x or PbTiO x .

18 . The fabricating method of an MIM capacitor of claim 10 , wherein the superlattice layer has a positive voltage coefficient of capacitance.

Assignees

• United Microelectronics Corp

Inventors

• Lin da-jun
• Tsai Bin-Siang
• Tsai Fu-Yu
• Chiu Chung-Yi

Classifications

• H10D1/692

  Electrodes · CPC title

• H10D1/684 Primary

  the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers · CPC title