Three-dimensional memory devices with channel structures having plum blossom shape

Patent metadata

Field	Value
Publication number	US-12532468-B2
Application number	US-202017112594-A
Country	US
Kind code	B2
Filing date	Dec 4, 2020
Priority date	Oct 19, 2020
Publication date	Jan 20, 2026
Grant date	Jan 20, 2026

Abstract

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a channel structure extending vertically above the substrate and having a plum blossom shape including a plurality of petals in a plan view. The channel structure includes, in each of the plurality of petals, a semiconductor channel and a channel plug above and in contact with the semiconductor channel.

First claim

What is claimed is:

1 . A three-dimensional (3D) memory device, comprising:
a substrate; and a channel structure extending vertically above the substrate and having a plum blossom shape comprising a plurality of petals in a plan view, wherein; the channel structure comprises, in each of the plurality of petals, a semiconductor channel and a channel plug above and in contact with the semiconductor channel; and the channel structure further comprises a memory film surrounding each semiconductor channel within the plurality of petals, the memory film extending continuously across the semiconductor channels in the plurality of petals.

2 . The 3D memory device of claim 1 , wherein a number of the petals is greater than 2.

3 . The 3D memory device of claim 1 , wherein the plurality of semiconductor channels are separated from one another, and the plurality of channel plugs are separated from one another.

4 . The 3D memory device of claim 1 , wherein a thickness of each of the plurality of semiconductor channels is nominally uniform in the plan view.

5 . The 3D memory device of claim 1 , wherein in each of the plurality of petals, a lateral dimension of the channel plug is greater than a lateral dimension of the semiconductor channel.

6 . The 3D memory device of claim 1 , wherein the channel the memory film comprises a blocking layer, a charge trapping layer, and a tunneling layer from outside to inside in this order in the plan view, and each of the blocking layer, the charge trapping layer, and the tunneling layer is a continuous layer following the plum blossom shape of the channel structure.

7 . The 3D memory device of claim 6 , wherein the channel structure further comprises, in each of the plurality of petals, a petal capping layer coplanar with the semiconductor channel, and the channel plug is laterally aligned with the semiconductor channel and the petal capping 3D .

8 . The 3D memory device of claim 7 , wherein a thickness of each of the plurality of petal capping layers is nonuniform in the plan view.

9 . The 3D memory device of claim 7 , further comprising a core capping layer filling a remaining space of the channel structure, wherein the petal capping layer and the core capping layer comprise different dielectric materials.

10 . The 3D memory device of claim 9 , wherein the blocking layer, the charge trapping layer, the tunneling layer, the semiconductor channel, the petal capping layer, and the core capping layer comprise silicon oxide, silicon nitride, silicon oxide, polysilicon, silicon nitride, and silicon oxide, respectively.

11 . The 3D memory device of claim 6 , wherein a thickness of each of the blocking layer, the charge trapping layer, and the tunneling layer is nominally uniform in the plan view.

12 . The 3D memory device of claim 6 , wherein each of the plurality of semiconductor channels is laterally disposed over part of the tunneling layer at an apex of a respective one of the petals.

13 . The 3D memory device of claim 1 , wherein the semiconductor channel and the channel plug comprise a same semiconductor material.

14 . The 3D memory device of claim 1 ,
each of the plurality of petals comprises an apex; and each apex of the plurality of petals comprises a curved shape.

15 . The 3D memory device of claim 1 , wherein:
the plurality of semiconductor channels are separated from one another at intersections where one petal of the plurality of petals intersects with another petal of the plurality of petals.

16 . The 3D memory device of claim 1 , wherein:
the plurality of channel plugs are separated from one another at intersections where one petal of the plurality of petals intersects with another petal of the plurality of petals.

17 . The 3D memory device of claim 1 , wherein:
the channel structure further comprises, in each of the plurality of petals, a petal capping layer over a respective semiconductor channel; and a thickness of one petal capping layer of the plurality of petal capping layers, in the plan view, is reduced from an apex of a corresponding petal of the plurality of petals toward an intersection where the petal and an adjacent petal intersect.

18 . The 3D memory device of claim 1 , wherein:
a thickness of one channel plug of the plurality of channel plugs, in the plan view, is reduced from an apex of a corresponding petal of the plurality of petals toward an intersection where the petal and an adjacent petal intersect.

19 . The 3D memory device of claim 1 , wherein:
one petal of the plurality of petals intersects with another petal of the plurality of petals at an intersection; and the intersection comprises a curved shape.

20 . The 3D memory device of claim 1 , wherein:
the channel structure further comprises, in each of the plurality of petals, a petal capping layer over a respective semiconductor channel; and one channel plug of the channel plugs is above and in contact with a corresponding petal capping layer of the plurality of petal capping layers.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Gao Tingting
• Xue Lei
• Liu Xiaoxin
• Geng Wanbo

Classifications

• H10D64/037 Primary

  comprising charge-trapping insulators · CPC title

• H10D30/694

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title