Semiconductor memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12532449-B2
Application number	US-202217847861-A
Country	US
Kind code	B2
Filing date	Jun 23, 2022
Priority date	Nov 22, 2019
Publication date	Jan 20, 2026
Grant date	Jan 20, 2026

Abstract

A semiconductor memory device includes a memory cell array of a three-dimensional structure including a plurality of memory cells repeatedly arranged in a first horizontal direction and a second horizontal direction that are parallel with a main surface of a substrate and cross each other on the substrate and in a vertical direction perpendicular to the main surface, wherein each of the plurality of memory cells includes three transistors. A method of manufacturing a semiconductor memory device includes forming simultaneously a plurality of memory cells arranged in a row in a vertical direction on a substrate, wherein each of the plurality of memory cells includes three transistors.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor memory device, the method comprising:
simultaneously forming a plurality of memory cells stacked on a substrate in a vertical direction, the plurality of memory cells arranged in a row, wherein each of the plurality of memory cells comprises three transistors and a bit line, the three transistors and the bit line arranged on a plane in a horizontal direction, the horizontal direction is parallel with an upper surface of the substrate, and the vertical direction is perpendicular to the upper surface of the substrate.

2 . The method of manufacturing of claim 1 , wherein the simultaneously forming of the plurality of memory cells comprises forming one read word line shared by the plurality of memory cells.

3 . The method of manufacturing of claim 1 , wherein the simultaneously forming of the plurality of memory cells comprises forming one write word line shared by the plurality of memory cells.

4 . The method of manufacturing of claim 1 , wherein the simultaneously forming of the plurality of memory cells comprises forming one storage node shared by the plurality of memory cells.

5 . A method of manufacturing a semiconductor memory device, the method comprising:
simultaneously forming a plurality of memory cells on a substrate in a vertical direction, the plurality of memory cells arranged in a row, wherein each of the plurality of memory cells comprises three transistors, and wherein the simultaneously forming of the plurality of memory cells comprises: forming a cell pattern in which a plurality of conductive layers and a plurality of intermediate insulating layers are alternately stacked on the substrate; replacing some regions of each of the plurality of conductive layers with a first channel region, a second channel region, and a third channel region; forming a read word line and a write word line, the read word line and the write word line extending in the vertical direction along a sidewall of the cell pattern; and replacing a portion of each of the plurality of conductive layers with a storage gate.

6 . The method of manufacturing of claim 5 , wherein, in the forming of the read word line and the write word line, the read word line is formed covering a first sidewall of the second channel region and a second sidewall of the second channel region, and the write word line is formed covering a first sidewall of the third channel region and a second sidewall of the third channel region.

7 . The method of manufacturing of claim 5 , wherein the simultaneously forming of the plurality of memory cells further comprises forming a plurality of source/drain regions, each of which is arranged on each of a first side of the first channel region, a second side of the first channel region, a first side of the second channel region, a second side of the second channel region, a first side of the third channel region, and a second side of the third channel region, the first channel region, the second channel region, and the third channel region from each of the plurality of conductive layers.

8 . The method of manufacturing of claim 5 , wherein the simultaneously forming of the plurality of memory cells further comprises forming a plurality of bit lines from a portion of each of the plurality of conductive layers.

9 . The method of manufacturing of claim 5 , wherein the simultaneously forming of the plurality of memory cells further comprises forming a storage node extending in the vertical direction along the sidewall of the cell pattern and facing each of the plurality of conductive layers.

10 . A method of manufacturing a semiconductor memory device, the method comprising:
alternately stacking a plurality of conductive layers and a plurality of intermediate insulating layers on a substrate; forming a cell pattern comprising a first line region and a second line region, the first line region and the second line region extending in a first horizontal direction, the first line region and the second line region being parallel with each other, the forming the cell pattern including removing a portion of each of the plurality of conductive layers and the plurality of intermediate insulating layers; in each of the plurality of conductive layers, replacing some regions included in the first line region and the second line region with a first channel region, a second channel region, and a third channel region; forming a read word line extending along a first sidewall of the cell pattern in a vertical direction and facing the second channel region; forming a write word line extending along a second sidewall of the cell pattern in the vertical direction and facing the third channel region; and in each of the plurality of conductive layers, replacing a portion of a conductive layer of the plurality of conductive layers that faces the first channel region with a storage gate.

11 . The method of manufacturing of claim 10 , wherein the forming of the read word line and the forming of the write word line are simultaneously performed.

12 . The method of manufacturing of claim 10 , wherein, in the forming of the cell pattern, the cell pattern is formed to further comprise a third line region extending in a second horizontal direction, the second horizontal direction perpendicular to the first horizontal direction, the third line region connected to the first line region and the second line region, and
the method of manufacturing further comprises forming a plurality of bit lines from portions included in the third line region among the plurality of conductive layers.

13 . The method of manufacturing of claim 10 , wherein each of the first channel region, the second channel region, and the third channel region comprises at least one of single crystal silicon, polysilicon, indium gallium zinc oxide (IGZO), indium tin gallium oxide (ITGO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium zinc oxide (IZO), or zinc tin oxide (ZTO).

14 . The method of manufacturing of claim 10 , further comprising:
forming a storage node extending in the vertical direction along a third sidewall of the cell pattern, the storage node facing the storage gate.

15 . The method of manufacturing of claim 10 , wherein, in the replacing of the some regions comprised in the first line region and the second line region with the first channel region, the second channel region, and the third channel region,
a plurality of second channel regions in the first line region that are arranged in the vertical direction in a row are formed by replacing some regions included in the first line region among the plurality of conductive layers with the second channel regions, and a plurality of third channel regions in the second line region that are arranged in the vertical direction in a row are formed by replacing some regions included in the second line region among the plurality of conductive layers with the third channel regions.

16 . The method of manufacturing of claim 10 , wherein, in the forming of the cell pattern, a length in the first horizontal direction of the first line region is different from a length in the first horizontal direction of the second line region.

17 . The method of manufacturing of claim 10 , wherein, in the forming of the cell pattern, a length in the first horizontal direction of the first line region is identical to a length in the first horizontal direction of the second line region, and the cell pattern comprises a portion having an H-shaped planar shape.

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Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Minsu
• Lee Kiseok
• Song Woobin
• Cho Minhee

Classifications

• H10B12/395 Primary

  the transistor being vertical · CPC title

• H10B12/50

  Peripheral circuit region structures · CPC title

• H10B12/056

  the transistor being a FinFET · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title