Combining sampling analog-to-digital converter with continuously integrating analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-12531566-B2
Application number	US-202318125668-A
Country	US
Kind code	B2
Filing date	Mar 23, 2023
Priority date	Mar 28, 2022
Publication date	Jan 20, 2026
Grant date	Jan 20, 2026

Abstract

A digitizing circuit includes a port connectable to a device under test (DUT), an integrating analog-to-digital converter (ADC), a high-speed ADC, one or more processors to apply a digital filter to output samples of the high-speed ADC to produce filtered samples, find differences between the filtered samples and samples from the integrating ADC to produce error values, and add the error values to the output samples of the high-speed ADC. A method of producing a digital signal includes receiving an input analog signal at an integrating analog-to-digital converter (ADC) and a high-speed ADC, applying a digital filter to output samples of the high-speed ADC to produce filtered samples, the digital filter matched to timing and filtering of the integrating ADC, finding differences between the filtered samples to output samples of the integrating ADC to produce error values, and adding the error values to the output samples of the high-speed ADC.

First claim

I claim:

1 . A digitizing circuit, comprising:
a port connectable to a device under test (DUT) to receive an input analog signal; an integrating analog-to-digital converter (ADC) coupled to the port to receive the input analog signal, wherein the integrating ADC comprises a digital filter; a high-speed ADC coupled to the port to receive the input analog signal, the high-speed ADC having a higher speed than the integrating ADC; and one or more processors configured to:
apply a digital filter to output samples of the high-speed ADC to produce filtered samples, wherein the digital filter approximately matches an aperture of the integrating ADC determined by the digital filter of the integrating ADC;
find differences between the filtered samples and output samples of the integrating ADC to produce error values based on a ratio of a sample rate of the integrating ADC to a sample rate of the high-speed ADC; and
add the error values to the output samples of the high-speed ADC to produce data samples of the input analog signal.

2 . The digitizing circuit as claimed in claim 1 , wherein the one or more processors are further configured to update the digital filter after each output sample of the integrating ADC.

3 . The digitizing circuit as claimed in claim 1 , wherein the one or more processors configured to find differences between the filtered samples and the output samples of the integrating ADC are further configured to:
subtract a filtered sample from an output sample of the integrating ADC to produce a difference; and
multiply the difference by the ratio of the sample rate of the integrating ADC to the sample rate of the high-speed ADC.

4 . The digitizing circuit as claimed in claim 1 , wherein the integrating ADC has an integration interval equal to an integer number of high-speed time positions of the high-speed ADC, and the integration interval applies to contiguous blocks of sampling time positions.

5 . The digitizing circuit as claimed in claim 1 , wherein the integrating ADC has an integration interval equal to a number of sampling time positions of the high-speed ADC, and the integration interval is a sliding window across the sampling time positions.

6 . The digitizing circuit as claimed in claim 1 , wherein the one or more processors are further configured to match offsets of the integrating ADC and the high-speed ADC.

7 . The digitizing circuit as claimed in claim 1 , wherein the one or more processors are further configured to match gains of the integrating ADC and the high-speed ADC.

8 . A method of producing a digital signal from an analog signal, comprising:
receiving an input analog signal at an integrating analog-to-digital converter (ADC) and a high-speed ADC having a higher speed than the integrating ADC, wherein the integrating ADC comprises a digital filter; applying a digital filter to output samples of the high-speed ADC to produce filtered samples, the digital filter being matched to an aperture of the integrating ADC determined by the digital filter of the integrating ADC; finding differences between the filtered samples and output samples of the integrating ADC to produce error values based on a ratio of a sample rate of the integrating ADC to a sample rate of the high-speed ADC; and adding the error values to the output samples of the high-speed ADC to produce data samples of the input analog signal.

9 . The method as claimed in claim 8 , further comprising updating the digital filter as necessary after each output sample of the integrating ADC.

10 . The method as claimed in claim 8 , wherein finding differences between the filtered samples and output samples of the integrating ADC comprises:
subtracting a filtered sample from an output sample of the integrated ADC; and
multiplying the difference by the ratio of the sample rate of the integrating ADC to the sample rate of the high-speed ADC.

11 . The method as claimed in claim 8 , wherein the integrating ADC has an integration interval equal to a number of sampling time positions of the high-speed ADC, and the integration interval applies to contiguous blocks of sampling time positions.

12 . The method as claimed in claim 8 , wherein the integrated ADC has an integration interval equal to a number of sampling time positions of the high-speed ADC, and the integration interval is a sliding window across the sampling time positions.

13 . The method as claimed in claim 8 , further comprising matching offsets of the integrating ADC and the high-speed ADC.

14 . The method as claimed in claim 13 , wherein matching offsets comprises setting a value of the input analog signal to zero and adjusting an offset of at least one of the integrating ADC and the high-speed ADC until the error values are zero.

15 . The method as claimed in claim 8 , further comprising matching gains of the integrating ADC and the high-speed ADC.

16 . The method as claimed in claim 15 , wherein matching gains comprises setting the input analog signal with enough amplitude sufficient to adjust the gain, and adjusting the gain of at least one of the integrating ADC and the high-speed ADC until the error values are zero.

17 . A circuit, comprising:
a port connectable to a device under test (DUT) to receive an input signal; a first analog-to-digital converter (ADC) coupled to the port to receive the input signal; a second ADC coupled to the port to receive the input signal, the second ADC having a higher speed than the first ADC; and one or more processors configured to:
apply a digital filter to output samples of the second ADC to produce filtered samples, the digital filter being matched to an aperture of the first ADC determined by a digital filter of the first ADC;
subtract the filtered samples from output samples of the first ADC to produce differences;
multiply the differences by a ratio of a sample rate of the first ADC to a sample rate of the second ADC to produce error values; and
add the error values to the output samples of the second ADC to produce data samples of the input signal.

18 . The circuit as claimed in claim 17 , wherein the first ADC has an integration interval equal to one of an integer number of high-speed time positions or a number of sampling time positions of the second ADC, and the integration interval applies to one of contiguous blocks of sampling time positions or a sliding window across the sampling time positions.

19 . The circuit as claimed in claim 17 , wherein the one or more processors are further configured to match at least one of gains or offsets of the first ADC and the second ADC.

20 . A method, comprising:
receiving an input analog signal at a first analog-to-digital converter (ADC) and a second ADC having a higher sample rate than the first ADC, wherein the first ADC comprises a digital filter; applying a digital filter to output samples of the second ADC to produce filtered samples, the digital filter being matched to an aperture of the first ADC determined by the digital filter of the first ADC; finding differences between the filtered samples and output samples of the first ADC to produce error values based on a ratio of a sample rate of the first ADC to a sample rate of the second ADC; and adding the error values to the output samples of the second ADC to produce data samples of the input analog signal.

Assignees

• Keithley Instruments

Inventors

• Goeke Wayne C

Classifications

• H03M1/0626 Primary

  by filtering · CPC title

• H03M1/126

  Multi-rate systems, i.e. adaptive to different fixed sampling rates · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/121

  Interleaved, i.e. using multiple converters or converter parts for one channel · CPC title

• H03M1/0675

  using redundancy · CPC title