Electronic device allocating data in plurality of caches using cache allocation range information

Patent metadata

Field	Value
Publication number	US-12530297-B2
Application number	US-202418607858-A
Country	US
Kind code	B2
Filing date	Mar 18, 2024
Priority date	Mar 24, 2023
Publication date	Jan 20, 2026
Grant date	Jan 20, 2026

Abstract

An electronic device including a main memory, a plurality of caches that are hierarchically connected, the plurality of caches configured to store part of data stored in the main memory, and processing circuitry configured to transmit a memory request for desired data to the plurality of caches and the main memory, the memory request including cache allocation range information associated with the desired data, and each of the plurality of caches are configured to, determine whether to perform an operation corresponding to the memory request based on the cache allocation range information.

First claim

What is claimed is:

1 . An electronic device comprising:
a main memory; a plurality of caches that are hierarchically connected, the plurality of caches each configured to store part of data stored in the main memory, the plurality of caches including an uppermost level cache in a closest proximity to processing circuitry and a lowermost level cache in a closest proximity to the main memory; and the processing circuitry configured to transmit a memory request for desired data to the uppermost level cache, the memory request including cache allocation range information associated with the desired data, and wherein each of the plurality of caches is configured to
determine whether to perform an operation corresponding to the memory request based on the cache allocation range information, and
wherein the cache allocation range information comprises
allocation start level information indicating a highest level cache among the plurality of caches in which the desired data corresponding to the memory request may be stored, and allocation end level information indicating a lowest level cache among the plurality of caches in which the desired data corresponding to the memory request may be stored.

2 . The electronic device of claim 1 , wherein the main memory is configured to store a page table including a plurality of page entries, each page entry of the plurality of page entries including cache allocation range information corresponding to data associated with the respective page entry.

3 . The electronic device of claim 2 , further comprising:
a Translation Look-aside Buffer (TLB) configured to store page entries corresponding to data accessed by the processing circuitry.

4 . The electronic device of claim 1 , wherein the processing circuitry is further configured to:
set the cache allocation range information based on any one of a delay time and throughput desired to process the memory request, the setting the cache allocation range information including, set the cache allocation range information to include the uppermost level cache of the plurality of caches based on the delay time desired for processing the memory request and a reference delay time, and set the cache allocation range information to include a least significant level cache of the plurality of caches based on the throughput desired for processing the memory request and a reference throughput.

5 . The electronic device of claim 1 , wherein the processing circuitry is further configured to set the cache allocation range information based on an intended usage of the desired data.

6 . The electronic device of claim 1 , wherein each of the plurality of caches is configured to:
in response to receiving the memory request, determine whether the desired data corresponding to the memory request may be stored therein based on the cache allocation range information; in response to determining that the desired data corresponding to the memory request may be stored therein, perform the operation corresponding to the memory request; and in response to determining that the desired data corresponding to the memory request may not be stored therein, not performing the operation corresponding to the memory request.

7 . The electronic device of claim 1 , wherein each of the plurality of caches is configured to:
in response to the memory request being a write request and determining that the desired data corresponding to the write request may be stored internally based on the cache allocation range information, store the desired data internally, and transmit the write request to a lower level cache of the plurality of caches or the main memory; and in response to the memory request being the write request and determining that the desired data corresponding to the write request may not be stored internally based on the cache allocation range information, transmit the write request to the lower level cache of the plurality of caches or the main memory.

8 . The electronic device of claim 7 , wherein a respective cache of the plurality of caches is configured to:
in response to the memory request being the write request and determining that the desired data corresponding to the write request may not be stored internally based on the cache allocation range information, search for invalid cache data corresponding to the write request in the respective cache; and in response to the invalid cache data corresponding to the write request being found in the respective cache, delete the invalid cache data corresponding to the write request.

9 . The electronic device of claim 8 , wherein each of the plurality of caches is configured to, in response to the invalid cache data corresponding to the desired data being found internally, write the desired data over the invalid cache data corresponding to the write request.

10 . The electronic device of claim 1 , wherein each of the plurality of caches is configured to:
in response to the memory request being a read request, search for the desired data corresponding to the read request internally; in response to the desired data not being found internally, transmit the read request to a lower level cache of the plurality of caches or the main memory; in response to the desired data being found internally, determine whether the desired data corresponding to the read request may be stored internally based on the cache allocation range information; in response to the desired data being stored internally, transmit the desired data to the processing circuitry; and in response to the desired data not being stored internally, transmit the desired data to the processing circuitry, and delete invalid cache data corresponding to the read request.

11 . The electronic device of claim 10 , wherein
the main memory is configured to,
in response to receiving the read request, transmit the read request and the cache allocation range information corresponding to the read request to the plurality of caches and the processing circuitry; and
each of the plurality of caches is configured to, in response to determining that the desired data may be stored internally based on the cache allocation range information corresponding to the read request,
store the desired data internally, and transmit the cache allocation range information corresponding to the desired data to a higher level cache of the plurality of caches or the processing circuitry, and
in response to determining that the desired data may not be stored internally based on the cache allocation range information corresponding to the read request,
transmit the desired data and the cache allocation range information corresponding to the desired data to the higher level cache of the plurality of caches or the processing circuitry.

12 . The electronic device of claim 1 , wherein the processing circuitry is further configured to:
store the cache allocation range information; and search for a cache among the plurality of caches which stores the desired data corresponding to the memory request based on the cache allocation range information.

13 . An electronic device comprising:
a main memory; a plurality of caches hierarchically connected, the plurality of caches each configured to store part of data stored in the main memory, the plurality of caches including an uppermost level cache in a closest proximity to processing circuitry and a lowermost level cache in a closest proximity to the main memory; and the processing circuitry configured to transmit a memory request for desired data to the uppermost level cache, the memory request including cach

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Moongyung
• Won Euiyeon
• Ham Donghyeon
• Eom Youngsik
• Cho Ara

Classifications

• G06F12/0811 Primary

  with multilevel cache hierarchies · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title