Memory system, storage system and method of controlling the memory system

Patent metadata

Field	Value
Publication number	US-10922240-B2
Application number	US-201916298529-A
Country	US
Kind code	B2
Filing date	Mar 11, 2019
Priority date	Sep 19, 2018
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

According to one embodiment, a memory system includes a cache configured to cache a part of a multi-level mapping table for logical-to-physical address translation, and a controller. The multi-level mapping table includes a plurality of hierarchical tables corresponding to a plurality of hierarchical levels. The table of each hierarchical level includes a plurality of address translation data portions. The controller sets a priority for each of the hierarchical level based on a degree of bias of reference for each of the hierarchical level, and preferentially caches each of the address translation data portions of a hierarchical level with a high priority into the cache, over each of the address translation data portions of a hierarchical level with low priority.

First claim

What is claimed is:

1. A memory system connectable to a host, comprising:
a nonvolatile memory configured to store a multi-level mapping table for logical-to-physical address translation;
a cache configured to cache a part of the multi-level mapping table; and
a controller configured to control the nonvolatile memory and the cache,
the multi-level mapping table including a plurality of tables corresponding to a plurality of hierarchical levels, each of the tables containing a plurality of address translation data portions, and each of the plurality of address translation data portions included in the table of each of the hierarchical levels covering a logical address range according to each hierarchical level, wherein
the controller is further configured to:
execute, by referring to the address translation data portion corresponding to each of the hierarchical levels stored in the cache, an address resolution process for the logical-to-physical address translation and an address update process of updating a physical address corresponding to a logical address;
obtain, for each of the hierarchical levels, a degree of bias of reference with respect to the address translation data portion stored in the cache;
set a priority for each of the hierarchical levels such that a high priority is set to a hierarchical level in which the degree of bias of reference is weak and a low priority is set to a hierarchical level in which the degree of bias of reference is strong, based on the degree of bias of reference for each of the hierarchical levels obtained; and
execute an operation of preferentially caching each of the address translation data portions of the hierarchical level with the high priority into the cache, over each of the address translation data portions of the hierarchical level with the low priority.

2. The memory system of claim 1 , wherein
the controller is further configured to preferentially cache each of the address translation data portions of the hierarchical level with the high priority into the cache, over each of the address translation data portions of the hierarchical level with the low priority, by preferentially selecting each of the address translation data portions of the hierarchical level with the low priority as a candidate for replacement target, over each of the address translation data portions of the hierarchical level with the high priority.

3. The memory system of claim 1 , wherein
the controller is further configured to not reflect a cache hit that occurred, in the address update process in a value indicating the degree of bias of reference for each of the hierarchical levels, when a reference tendency of the cache resulting from write access by the host is to be neglected.

4. The memory system of claim 1 , wherein
the controller is further configured to not reflect a cache hit that occurred in the address resolution process in a value indicating the degree of bias of reference for each hierarchical level, when a reference tendency of the cache resulting from read access by the host is to be neglected.

5. The memory system of claim 1 , wherein the controller is further configured to:
control a plurality of caches, each configured to cache a part of a corresponding multi-level mapping table of a plurality of multi-level mapping tables corresponding to a plurality of namespaces;
regarding each of the plurality of caches, obtain, for each of the hierarchical levels, a degree of bias of reference with respect to the address translation data portion stored in each cache; and
execute, based on the degree of bias of reference for each of the hierarchical levels obtained, an operation of setting a priority for each of the hierarchical levels and an operation of preferentially caching each of the address translation data portions of the hierarchical level with a high priority into a corresponding cache, over each of the address translation data portions of the hierarchical level with a low priority, for each cache.

6. The memory system of claim 1 , wherein
the controller is further configured to adjust a size of each of the plurality of caches, based on at least one of (i) a frequency of access to each of the plurality of name spaces by the host, and (ii) the degree of bias of reference for each of the hierarchical levels corresponding to each cache.

7. A storage system connectable to a host, comprising:
a plurality of storage devices;
a cache configured to cache a part of a mapping table which manages mapping between each of first type logical addresses designated by the host and each of second type logical addresses for accessing the plurality of storage devices; and
a controller configured to control the plurality of storage devices and the cache,
the multi-level mapping table including a plurality of tables corresponding to a plurality of hierarchical levels, each of the tables containing a plurality of address translation data portions, and each of the plurality of address translation data portions included in the table of each of the hierarchical levels covering a logical address range according to each hierarchical level, wherein
the controller is further configured to:
execute, by referring to the address translation data portion corresponding to each of the hierarchical levels stored in the cache, an address resolution process for converting the first type logical address into the second type logical address and an address update process of updating the second type logical address;
obtain, for each of the hierarchical levels, a degree of bias of reference with respect to the address translation data portion stored in the cache;
set a priority for each of the hierarchical levels such that a high priority is set to a hierarchical level in which the degree of bias of reference is weak and a low priority is set to a hierarchical level in which the degree of bias of reference is strong, based on the degree of bias of reference for each of the hierarchical levels obtained; and
execute an operation of preferentially caching each of the address translation data portions of the hierarchical level with the high priority into the cache, over each of the address translation data portions of the hierarchical level with the low priority.

8. The storage system of claim 7 , wherein
the controller is further configured to preferentially cache each of the address translation data portions of the hierarchical level with the high priority into the cache, over each of the address translation data portions of the hierarchical level with the low priority, by selecting each of the address translation data portions of the hierarchical level with the low priority as a candidate for replacement target, over each of the address translation data portions of the hierarchical level with the high priority.

9. The storage system of claim 7 , wherein the controller is further configured to:
control a plurality of caches, each configured to cache a part of a corresponding multi-level mapping table of a plurality of multi-level mapping tables corresponding to a plurality of namespaces;
regarding each of the plurality of caches, obtain, for each of the hierarchical levels, a degree of bias of reference with respect to the address translation data portion stored in each cache; and
execute, based on the degree of bias of reference for each of the hierarchical levels obtained, an operation of setting a priority for each of the hierarchical levels and an operation of preferentially caching each of the address translation data portion of the hierarchical level with a high priority into a corresponding cache, over each of the address translation data portions of the hierarchical level with a low priority, for each cache.

Assignees

• Toshiba Memory Corp

Inventors

• Onishi Shohei
• Saito Yoshiki
• Hasegawa Yohei
• Watanabe Konosuke

Classifications

• G06F2212/608

  Details relating to cache mapping · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title