Task scheduling for systems including multiple hardware accelerators

Patent metadata

Field	Value
Publication number	US-12530233-B2
Application number	US-202318175333-A
Country	US
Kind code	B2
Filing date	Feb 27, 2023
Priority date	May 26, 2022
Publication date	Jan 20, 2026
Grant date	Jan 20, 2026

Abstract

A data processing device includes a plurality of hardware accelerators, a scheduler circuit, and a blocking circuit. The scheduler circuit is coupled to the plurality of hardware accelerators, and includes a plurality of hardware task schedulers. Each hardware task scheduler is coupled to a corresponding hardware accelerator, and is configured to control execution of the task by the hardware accelerator. The blocking circuit is coupled to the plurality of hardware accelerators and configured to inhibit communication between a first hardware accelerator and a second hardware accelerator of the plurality of hardware task schedulers.

First claim

What is claimed is:

1 . A data processing device comprising:
first, second, and third hardware accelerator sets, wherein each of the first, second, and third hardware accelerator sets include one or more hardware accelerators; and a scheduler circuit coupled to the first, second, and third hardware accelerator sets, wherein:
the scheduler circuit includes a first hardware task scheduler circuit coupled to the first hardware accelerator set, a second hardware task scheduler circuit coupled to the second hardware accelerator set, and a third hardware task scheduler circuit coupled to the third hardware accelerator set;
the first hardware task scheduler circuit includes:
a first output circuit configured to provide a first signal to an input circuit of the second hardware task scheduler circuit, wherein the first signal indicates that a first set of data produced by the first hardware accelerator set is available for the second hardware accelerator set; and
a first blocking circuit configured to inhibit communication of the first signal when the first set of data is available based on a status of the second hardware accelerator set; and

the second hardware task scheduler circuit includes;
a second output circuit configured to provide a second signal to an input circuit of a third hardware task scheduler circuit, wherein the second signal indicates that a second set of data produced by the second hardware accelerator set using the first set of data is available for the third hardware accelerator set; and
a second blocking circuit configured to inhibit communication of the second signal when the second set of data is available based on a status of the third hardware accelerator set.

2 . The data processing device of claim 1 , wherein the first hardware task scheduler circuit further includes a clear block pending circuit configured to cause the first blocking circuit to stop inhibiting communication of the first signal based at least in part on completion of a corresponding task by the second hardware accelerator set.

3 . The data processing device of claim 1 , wherein:
the first signal is a first pending signal; the first hardware task scheduler circuit includes an input circuit configured to receive a second pending signal; and the first hardware task scheduler circuit is configured to cause the first hardware accelerator set to start execution of a corresponding task based on the second pending signal.

4 . The data processing device of claim 1 , wherein the data processing device is comprised in a multiprocessor system-on-a-chip.

5 . The data processing device of claim 1 , wherein one or more of the first, second, or third hardware accelerator sets is a processor and is configured to perform a corresponding task that comprises executing software instructions.

6 . The data processing device of claim 1 further comprising a memory mapped register that includes a first field, wherein the first blocking circuit is configured to inhibit communication of the first signal based on a value stored in the first field.

7 . The data processing device of claim 6 , wherein the memory mapped register includes a second field that indicates whether the first blocking circuit is currently inhibiting communication of the first signal.

8 . The data processing device of claim 1 further comprising a memory coupled to the first and second hardware accelerator sets, wherein the first signal indicates that the first set of data is available in the memory.

9 . The data processing device of claim 1 , wherein the third hardware accelerator set is subsequent to the first and second hardware accelerator sets in a pipeline.

10 . The data processing device of claim 1 , wherein:
the first hardware task scheduler circuit includes:
a set of inputs each configured to receive a respective signal indicating that a respective set of data is available; and
a set of outputs housed by the first output circuit, each configured to provide a respective signal that indicates that a respective set of data is available;
the second hardware task scheduler circuit includes:
a set of inputs housed by the input circuit of the second hardware task scheduler circuit, each configured to receive a respective signal that indicates that a respective set of data is available; and
a set of outputs housed by the second output circuit, each configured to provide a respective signal indicating that a respective set of data is available; and
the data processing device further comprises a crossbar coupled to the set of inputs and the set of outputs of the first hardware task scheduler circuit and coupled to the set of inputs and the set of outputs of the second hardware task scheduler circuit.

11 . A data processing device comprising:
first, second, and third hardware accelerator sets, wherein each of the first, second, and third hardware accelerator sets include one or more hardware accelerators; and a scheduler circuit comprising a first hardware task scheduler circuit coupled to the first hardware accelerator set, a second hardware task scheduler circuit coupled to the second hardware accelerator set, and a third hardware task scheduler circuit coupled to the third hardware accelerator set, wherein:
the first hardware task scheduler circuit includes:
a first output circuit configured to provide a first signal to an input circuit of the second hardware task scheduler circuit, wherein the first signal indicates that a first set of data produced by the first hardware accelerator set is available; and
a first blocking circuit configured to inhibit communication of the first signal when the first set of data is available based on a status of the second hardware accelerator set; and

the second hardware task scheduler circuit includes:
a second output circuit configured to provide a second signal to an input circuit of a third hardware task scheduler circuit, wherein the second signal indicates that a second set of data produced by the second hardware accelerator set using the first set of data is available for the third hardware accelerator set; and
a second blocking circuit configured to inhibit communication of the second signal when the second set of data is available based on a status of the third hardware accelerator set

wherein the scheduler circuit is configured to concurrently control the one or more hardware accelerators of the first hardware accelerator set to execute one or more first tasks and the one or more hardware accelerators of the second hardware accelerator set to execute one or more second tasks.

12 . The data processing device of claim 11 , wherein the first hardware task scheduler circuit further includes:
a clear block pending circuit configured to cause the first blocking circuit to stop inhibiting communication of the first signal based at least in part on completion of a corresponding task by the second hardware accelerator set.

13 . The data processing device of claim 11 , wherein:
the first signal is a first pending signal; the first hardware task scheduler circuit includes an input configured to receive a second pending signal; and the first hardware task scheduler circuit is configured to cause the one or more hardware accelerators of the first hardware accelerator set to start execution of the one or more first tasks based on the second pending signal.

14 . The data processing device of claim 11 , wherein the data processing device is comprised in a multiprocessor system-on-a-chip.

15 . The data processing device of claim 11 , wherein one or more of the first, second, and third

Assignees

• Texas Instruments Inc

Inventors

• Mody Mihir
• Nandan Niraj
• Allu Rajasekhar
• Ankur Ankur

Classifications

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/544

  Buffers; Shared memory; Pipes · CPC title

• G06F2209/483

  Multiproc · CPC title

• G06F2209/509

  Offload · CPC title

• G06F2209/5018

  Thread allocation · CPC title