Updating Hardware with Reduced Virtual Machine Downtime

Patent metadata

Field	Value
Publication number	US-2020257547-A1
Application number	US-201916271509-A
Country	US
Kind code	A1
Filing date	Feb 8, 2019
Priority date	Feb 8, 2019
Publication date	Aug 13, 2020
Grant date	—

Abstract

A technique is described herein for updating the logic used by a hardware accelerator provided by a computing device. In one implementation, the technique provides a pass-through mode which allows a virtual machine (provided by the computing device) to directly interact with the hardware accelerator. Upon the commencement of an updating operation, the technique instructs an emulator to begin emulating the function(s) of the hardware accelerator and the resultant effects of these functions, without interaction with the actual hardware accelerator. When the updating operation finishes, the technique re-enables the pass-through mode. By virtue of the above-summarized manner of operation, the technique allows the computing device to perform the function(s) associated with the hardware accelerator while the hardware accelerator is being updated. In one case, the technique disables the pass-through mode by modifying address-mapping information used by the virtual machine to access system physical addresses.

First claim

What is claimed is:

1 . A computing device for updating logic in a hardware accelerator, comprising:
hardware resources including a reconfigurable hardware accelerator; a privileged domain component having privileged access to the hardware resources; and a hypervisor for providing a virtual machine, in a pass-through mode of operation, the computing device enabling the virtual machine to directly interact with the hardware accelerator to pass information to and/or from the hardware accelerator, the hardware resources including hardware logic circuitry that is configured to perform operations including:
receiving logic for use in updating the hardware accelerator;
disabling the pass-through mode in response to receiving the logic;
transferring state information associated with the hardware accelerator into an emulator that is configured to emulate performance of the hardware accelerator;
commencing updating the hardware accelerator based on the logic that has been received; and
using the emulator to emulate one or more functions of the hardware accelerator while the hardware accelerator is being updated, instead of using the virtual machine to directly interact with the hardware accelerator in the pass-through mode.

2 . The computing device of claim 1 , wherein the computing device hosts plural virtual machines, each having a respective virtual machine address space.

3 . The computing device of claim 1 , wherein the logic includes:
machine-readable instructions to be installed on the hardware accelerator; and/or data for use in configuring a collection of gates provided by the hardware accelerator.

4 . The computing device of claim 1 , wherein:
the hardware accelerator is a storage controller for storing information in one or more storage devices, and/or retrieving information from said one or more storage devices, and said one or more functions, when emulated by the emulator, involve interacting with the said one or more storage devices without use of the hardware accelerator.

5 . The computing device of claim 1 , wherein:
the hardware accelerator is a network adapter for transmitting information over a computer network, and/or retrieving information from the computer network, and said one or more functions, when emulated by the emulator, involve interacting with the computer network without use of the hardware accelerator.

6 . The computing device of claim 1 , wherein the hardware accelerator performs:
a graphics processing function; and/or an encryption and/or decryption function; and/or a compression and/or decompression function.

7 . The computing device of claim 1 , wherein the state information specifies information retained in memory provided by the hardware accelerator, the information retained in memory defining a current state of operation of the hardware accelerator.

8 . The computing device of claim 1 , wherein:
the virtual machine is associated with a virtual machine address space, in the pass-through mode of operation, the virtual machine relies on address-mapping information which maps the virtual machine address space to valid system physical addresses, and said disabling comprises modifying the address-mapping information associated with the virtual machine so that the address-mapping information can no longer be relied on to point to valid system physical addresses, to provide updated map information.

9 . The computing device of claim 8 , wherein the updated address-mapping information disables access by the virtual machine to all functions performed by the hardware accelerator.

10 . The computing device of claim 8 , wherein the updated address-mapping information disables access by the virtual machine to one or more functions performed by the hardware accelerator, but not all of the functions performed by the hardware accelerator.

11 . The computing device of claim 1 , wherein said using the emulator comprises, according to one instance:
receiving a request by the virtual machine to access a system physical address; determining, based on current address-mapping information provided by the computing device, that the system physical address cannot be accessed; in response to said determining, instructing the emulator to emulate a function performed by the hardware accelerator; and in response to said instructing, emulating the function performed by the hardware accelerator, and emulating one or more effects produced as a result of performing the function.

12 . The computing device of claim 1 , wherein the operations further comprise:
receiving an indication that said updating performed by the hardware accelerator has finished; transferring state information provided by the emulator to the hardware accelerator; and re-enabling the pass-through mode.

13 . The computing device of claim 12 , wherein the operations further comprise pausing the virtual machine each time the address-mapping information is altered.

14 . A method for updating logic in a hardware accelerator, comprising:
receiving logic by a computing device, the computing device having:
hardware resources including a reconfigurable hardware accelerator;
a privileged domain component having privileged access to the hardware resources; and
a hypervisor for providing a virtual machine,
in a pass-through mode of operation, the computing device enabling the virtual machine to directly interact with the hardware accelerator to pass information to and/or from the hardware accelerator;
disabling the pass-through mode in response to receiving the logic; transferring state information associated with the hardware accelerator to an emulator that is configured to emulate performance of the hardware accelerator; commencing updating the hardware accelerator based on the logic that has been received; using the emulator to emulate one or more functions of the hardware accelerator while the hardware accelerator is being updated, instead of using the virtual machine to directly interact with the hardware accelerator in the pass-through mode; receiving an indication that said updating performed by the hardware accelerator has finished; transferring state information provided by the emulator to the hardware accelerator; and re-enabling the pass-through mode.

15 . The method of claim 14 , wherein:
the virtual machine is associated with a virtual machine address space, in the pass-through mode of operation, the virtual machine relies on address-mapping information which maps the virtual machine address space to valid system physical addresses, said disabling comprises modifying the address-mapping information associated with the virtual machine so that the address-mapping information can no longer be relied on to point to valid system physical addresses, and said re-enabling comprises changing the address-mapping information so that the address-mapping information can once again be relied on to point to valid system physical addresses.

16 . The method of claim 14 , wherein said using the emulator comprises, in one instance:
receiving a request by the virtual machine to access a system physical address; determining, based on current address-mapping information provided by the computing device, that the system physical address cannot be accessed; in response to said determining, instructing the emulator to emulate a function performed by the hardware accelerator; and in response to said instructing, emulating the function performed by the hardware accelerator, and emulating one or more effects produced as a result of performing the funct

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Oshins Jacob Kappeler
• Makhervaks Vadim

Classifications

• G06F2009/45595

  Network integration; Enabling network access in virtual machine instances · CPC title

• G06F2009/45583

  Memory management, e.g. access or allocation · CPC title

• G06F9/45508

  Runtime interpretation or emulation, e g. emulator loops, bytecode interpretation · CPC title

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title