Method of performing inter-site backup processing of wafer lots

US12529567B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12529567-B2
Application numberUS-202217855075-A
CountryUS
Kind codeB2
Filing dateJun 30, 2022
Priority dateJun 30, 2022
Publication dateJan 20, 2026
Grant dateJan 20, 2026

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  1. Title

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A method includes: receiving an auxiliary routing request from a manufacturing execution system (MES) apparatus of a first site by an inter-site backup management apparatus; selecting an auxiliary route to a second site based on the auxiliary routing request and a statistical model by the inter-site backup management apparatus; including the auxiliary route in a route associated with a wafer lot by the MES apparatus; and performing a semiconductor processing operation on a wafer of the wafer lot according to the route.

First claim

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What is claimed is: 1 . A method, comprising: receiving an auxiliary routing request from a manufacturing execution system (MES) apparatus of a first site by an inter-site backup management apparatus; selecting an auxiliary route to a second site based on the auxiliary routing request and a statistical model by the inter-site backup management apparatus; including the auxiliary route in a route associated with a wafer lot by the MES apparatus; and performing a semiconductor processing operation on a wafer of the wafer lot according to the route, wherein the auxiliary route includes transferring the wafer lot through a stocker that is accessible by both a first automatic material handling system (AMHS) apparatus of the first site and a second AMHS apparatus of the second site, the stocker including a conveyor apparatus having a defined loading capacity, and wherein selecting the auxiliary route comprises accounting for said loading capacity when determining whether the stocker is available to receive the wafer lot. 2 . The method of claim 1 , wherein the auxiliary route is selected based on a loading index associated with the second site. 3 . The method of claim 2 , wherein the loading index includes a number of wafer lots in process, an accumulated number of moves, a target move, an automatic material handling system (AMHS) loading, or a combination thereof. 4 . The method of claim 1 , wherein the auxiliary route is selected based on a priority level, a quality time, a cycle time, or combination thereof. 5 . The method of claim 1 , wherein the auxiliary route is selected based on a product constraint, a process constraint, a rework constraint, a tool constraint, a tool maintenance cycle, or combination thereof. 6 . The method of claim 1 , wherein the auxiliary route is selected based on transportation vehicle loading, traffic jam data, weather forecast data, power outage data, or a combination thereof. 7 . The method of claim 1 , further comprising: generating the statistical model by training a neural network. 8 . A method, comprising: generating or updating a statistical model for selecting an auxiliary route from a first site to a second site in a semiconductor manufacturing environment, including receiving training set data describing historical routing conditions; receiving, by an inter-site backup management apparatus, an auxiliary routing request from a manufacturing execution system (MES) apparatus of the first site for a wafer lot; selecting, by the inter-site backup management apparatus, the auxiliary route based on the statistical model; including the auxiliary route in a route associated with the wafer lot by the MES apparatus; and performing a semiconductor processing operation on the wafer lot according to the route, including transferring the wafer lot from the first site to the second site, wherein transferring the wafer lot from the first site to the second site comprises verifying that a stocker interconnecting the first site and the second site is below a threshold loading capacity. 9 . The method of claim 8 , further comprising generating the training set data from historical conditions data including at least one of: traffic conditions, weather forecasts, or an accumulated number of moves for the wafer lot. 10 . The method of claim 9 , wherein the statistical model comprises a neural network trained to reduce a difference between a predicted cycle time for the wafer lot and an actual cycle time for the wafer lot. 11 . The method of claim 8 , wherein selecting the auxiliary route is further based on a capacity constraint of a stocker accessible by both an automatic material handling system (AMHS) apparatus of the first site and an AMHS apparatus of the second site. 12 . The method of claim 8 , further comprising forecasting an inter-site backup process cycle time based on the statistical model, wherein selecting the auxiliary route is based at least in part on reducing the forecasted inter-site backup process cycle time. 13 . The method of claim 8 , wherein the auxiliary routing request includes a priority level and a quality time constraint for the wafer lot, and wherein selecting the auxiliary route comprises satisfying the quality time constraint for the wafer lot based on the priority level. 14 . The method of claim 8 , further comprising transferring the wafer lot from the first site to the second site via a sky bridge interconnected with overhead hoist transport tracks of the first site and the second site. 15 . A method, comprising: performing a first semiconductor processing operation on a wafer lot at a first site; determining, by a manufacturing execution system (MES) apparatus, that the wafer lot should be routed to a second site for a subsequent semiconductor processing operation; sending, by the MES apparatus to an inter-site backup management apparatus, an auxiliary routing request; selecting, by the inter-site backup management apparatus, an auxiliary route to the second site based on a statistical model trained with historical routing data; transferring the wafer lot to the second site according to the auxiliary route; and performing the subsequent semiconductor processing operation on the wafer lot at the second site, wherein transferring the wafer lot to the second site comprises verifying that a stocker interconnecting the first site and the second site is below a threshold loading capacity. 16 . The method of claim 15 , wherein the auxiliary routing request includes an indication that a scheduled tool maintenance at the first site would cause a delay exceeding a quality time threshold for the wafer lot. 17 . The method of claim 15 , wherein the threshold loading capacity is determined as a number of wafer lots transferred through the stocker during a selected time interval. 18 . The method of claim 15 , wherein the auxiliary routing request includes an indication that a process constraint at the first site would cause a delay exceeding a quality time threshold for the wafer lot. 19 . The method of claim 18 , wherein the process constraint comprises at least one of: a scheduled tool maintenance at the first site, a rework constraint, or an AMHS loading constraint. 20 . The method of claim 15 , wherein selecting the auxiliary route is further based on at least one of traffic jam data, weather forecast data, or power outage data stored in a database accessible by the inter-site backup management apparatus.

Assignees

Inventors

Classifications

  • Generating training patterns; Bootstrap methods, e.g. bagging or boosting · CPC title

  • employing speed data or traffic data, e.g. real-time or historical (traffic control systems for road vehicles involving transmission of navigation instructions to the vehicle G08G1/0968) · CPC title

  • Architecture, e.g. interconnection topology · CPC title

  • Production flow monitoring, e.g. for increasing throughput · CPC title

  • Resources, workflows, human or project management; Enterprise or organisation planning; Enterprise or organisation modelling · CPC title

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What does patent US12529567B2 cover?
A method includes: receiving an auxiliary routing request from a manufacturing execution system (MES) apparatus of a first site by an inter-site backup management apparatus; selecting an auxiliary route to a second site based on the auxiliary routing request and a statistical model by the inter-site backup management apparatus; including the auxiliary route in a route associated with a wafer lo…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd, Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification G01C21/3415. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 20 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).