Display panel and display apparatus

Patent metadata

Field	Value
Publication number	US-12527178-B2
Application number	US-202117921269-A
Country	US
Kind code	B2
Filing date	Oct 28, 2021
Priority date	Apr 23, 2021
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

Provided is a display panel. The display panel includes a base substrate, a plurality of dummy electrode patterns and a plurality of first connection traces. The dummy electrode patterns are disposed in a first display region of the base substrate, and the dummy electrode patterns and the first connection traces are disposed in different layers.

First claim

What is claimed is:

1 . A display panel, provided with a display region and a non-display region disposed on a periphery of the display region, the display panel comprising:
a base substrate comprising a first display region and a second display region, the first display region and the second display region being adjacent to each other; a plurality of first light-emitting units disposed in the first display region, wherein each of the plurality of first light-emitting unit includes an anode, a light-emitting layer and a cathode sequentially stacked in a direction away from the base substrate, and the plurality of first light-emitting units include a plurality of first light-emitting units of a first color, a plurality of first light-emitting units of a second color and a plurality of first light-emitting units of a third color, at least one first light-emitting unit of the first color, at least one first light-emitting unit of the second color and at least one first light-emitting unit of the third color constitute one light-emitting unit group; a plurality of first pixel circuit groups disposed in the first display region, each of the first pixel circuit groups being electrically connected to at least one of the first light-emitting units; a plurality of second light-emitting units disposed in the second display region; a plurality of second pixel circuit groups disposed in the first display region; a plurality of dummy electrode patterns disposed in the first display region, wherein the plurality of dummy electrode patterns are disposed in a same layer as the anode, the plurality of dummy electrode patterns constitute at least one dummy electrode pattern group, the number of the dummy electrode patterns in each dummy electrode pattern group is equal to the number of the first light-emitting units in one light-emitting unit group, the plurality of dummy electrode patterns in each dummy electrode pattern group are in one-to-one correspondence with the plurality of first light-emitting units in one light-emitting unit group, and each dummy electrode pattern in the dummy electrode pattern group has a same shape and area as the anode in the corresponding first light-emitting unit in the light-emitting unit group; and a plurality of first connection traces, at least one of the first connection traces having one end electrically connected to at least one of the second light-emitting units, and having the other end electrically connected to the dummy electrode patterns and the second pixel circuit groups; wherein the first connection traces and the dummy electrode patterns are disposed in different layers.

2 . The display panel according to claim 1 , further comprising: a plurality of second connection traces; wherein
at least one of the second connection traces has one end electrically connected to at least one of the second light-emitting units, and has the other end electrically connected to the dummy electrode patterns and the second pixel circuit groups; and the second connection traces, the first connection traces, and the dummy electrode patterns are disposed in different layers.

3 . The display panel according to claim 2 , wherein a sum of numbers of the first and second connection traces in the display panel is equal to a number of the dummy electrode patterns, the first connection traces and the second connection traces are in one-to-one correspondence with the dummy electrode patterns, and each of the first and second connection traces is electrically connected to a corresponding dummy electrode pattern of the dummy electrode patterns.

4 . The display panel according to claim 2 , wherein at least one of the dummy electrode patterns comprises a main body portion and a first connection portion, the first connection portion extending in a first direction, and both the first connection traces and the second connection traces extend in a second direction, the first direction being intersected with the second direction;
wherein the first connection portion is electrically connected, at an intersection of the first connection portion and at least one of the first and second connection traces, to the at least one of the first and second connection traces by a via.

5 . The display panel according to claim 4 , wherein each of the second pixel circuit groups comprises: a source-drain metal layer disposed on the base substrate, the source-drain metal layer comprising a source and a drain spaced apart; and the display panel further comprises: a first insulation layer, a second insulation layer, and a third insulation layer;
wherein the source-drain metal layer, the first insulation layer, the first connection traces, the second insulation layer, the second connection traces, the third insulation layer, and the dummy electrode patterns are sequentially stacked in a direction going away from the base substrate.

6 . The display panel according to claim 2 , further comprising: a plurality of second connection portions, wherein the second connection portions extend in a first direction, the first connection traces and the second connection traces both extend in a second direction, and the first direction is intersected with the second direction; and
the second connection portions and the dummy electrode patterns are disposed in different layers, the second connection portions are electrically connected to one of the dummy electrode patterns by a via, and the second connection portions are further electrically connected, at an intersection of the second connections and at least one of the first and second connection traces, to the at least one of the first and second connection traces by a via.

7 . The display panel according to claim 6 , wherein each of the second pixel circuit groups comprises: a source-drain metal layer disposed on the base substrate, the second connection portions and the source-drain metal layer being disposed in a same layer.

8 . The display panel according to claim 6 , wherein
an orthographic projection of the intersection on the base substrate is not overlapped with an orthographic projection of any one of the dummy electrode patterns on the base substrate; or an orthographic projection of the intersection on the base substrate is within an orthographic projection of one of the dummy electrode patterns on the base substrate.

9 . The display panel according to claim 2 , wherein each of the second pixel circuit groups comprises: a source-drain metal layer disposed on the base substrate, the source-drain metal layer comprising a source and a drain spaced apart; and the display panel further comprises: a first insulation layer, a second insulation layer and a third insulation layer; wherein
the source-drain metal layer, the first insulation layer, the first connection traces, the second insulation layer, the second connection traces, the third insulation layer, and the dummy electrode patterns are sequentially stacked in a direction going away from the base substrate; the second insulation layer being provided with a plurality of seventh vias and a plurality of eighth vias, and the third insulation layer being provided with a plurality of ninth vias and a plurality of tenth vias, the ninth vias being in one-to-one correspondence with the seventh vias, and the tenth vias being in one-to-one correspondence with the eighth vias; wherein an orthographic projection of each of the seventh vias on the base substrate is at least partially overlapped with an orthographic projection of the corresponding ninth via on the base substrate, each of the seventh vias is configured to expose one of the first connection traces, and a first electrode of at least one of the second light-emitting units is electrically connecte

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Huang Yao
• Wang Binyan
• Qiu Yuanyou
• Liu Cong
• Wu Chao

Classifications

• H10K59/00

  Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00 · CPC title

• H10K59/88

  Dummy elements, i.e. elements having non-functional features · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/122 Primary

  Pixel-defining structures or layers, e.g. banks · CPC title