Display panel and manufacturing method thereof, and display device

Patent metadata

Field	Value
Publication number	US-11211012-B2
Application number	US-202017040340-A
Country	US
Kind code	B2
Filing date	Apr 20, 2020
Priority date	Jun 26, 2019
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

A display panel, a manufacturing method thereof and a display device are disclosed. The display panel includes: a display region including at least one rounded corner; and a non-display region located at a periphery of the display region. The non-display region includes: a gate drive circuit; and a plurality of first dummy pixels located outside the at least one rounded corner of the display region, a first power line of each of the plurality of the first dummy pixels being connected with a signal line of the gate drive circuit.

First claim

What is claimed is:

1. A display panel, comprising:
a display region, comprising at least one rounded corner; and
a non-display region, located at a periphery of the display region, and the non-display region comprising:
a gate drive circuit;
a plurality of first dummy pixels, located outside the at least one rounded corner of the display region, a first power line of each of the plurality of the first dummy pixels being connected with a signal line of the gate drive circuit; and
a plurality of second dummy pixels, provided at an opposite side of the display region to a bonding region,
wherein each of the plurality of the first dummy pixels and each of the plurality of the second dummy pixels at least respectively comprises a pixel drive circuit, the pixel drive circuit comprises a first scanning line, a second scanning line, and a third scanning line, and
wherein the first scanning line, the second scanning line, and the third scanning line are connected with the gate drive circuit respectively, or the first scanning line, the second scanning line, and the third scanning line are in a floating state.

2. The display panel according to claim 1 , wherein each of the plurality of the first dummy pixels is located between the gate drive circuit and the display region, and each of the plurality of the first dummy pixels is configured to not emit light.

3. The display panel according to claim 2 , wherein the plurality of the first dummy pixels are arranged as a step shape.

4. The display panel according to claim 2 ,
wherein the bonding region is located at one of sides of the display region, the plurality of second dummy pixels are provided at an opposite side of the display region to the bonding region, and each of the plurality of the second dummy pixels is configured not to emit light.

5. The display panel according to claim 3 , wherein the plurality of the first dummy pixels comprise at least one column in a first direction and at least one row in a second direction, and the first direction and the second direction are perpendicular to each other.

6. The display panel according to claim 3 ,
wherein the bonding region is located at one of sides of the display region, the plurality of second dummy pixels are provided at an opposite side of the display region to the bonding region, and each of the plurality of the second dummy pixels is configured not to emit light.

7. The display panel according to claim 1 ,
wherein the bonding region is located at one of sides of the display region, the plurality of second dummy pixels are provided at an opposite side of the display region to the bonding region, and each of the plurality of the second dummy pixels is configured not to emit light.

8. The display panel according to claim 7 , wherein a second power line of each of the plurality of the second dummy pixels is connected with the signal line of the gate drive circuit.

9. The display panel according to claim 7 , wherein the plurality of the second dummy pixels are arranged at equal intervals in at least one direction selected from the group consisting of a first direction and a second direction, and the first direction and the second direction are perpendicular to each other.

10. The display panel according to claim 9 , wherein the plurality of the second dummy pixels comprise at least one column in the first direction and at least one row in the second direction.

11. The display panel according to claim 7 , wherein the at least one rounded corner comprises:
a first rounded corner and a second rounded corner which are proximal to the bonding region, and the plurality of the first dummy pixels are arranged outside the first rounded corner and outside the second rounded corner.

12. The display panel according to claim 11 , wherein the at least one rounded corner further comprises:
a third rounded corner and a fourth rounded corner which are distal to the bonding region, and the plurality of the first dummy pixels are arranged outside the third rounded corner and outside the fourth rounded corner.

13. The display panel according to claim 1 , wherein each of the plurality of the first dummy pixels and each of the plurality of the second dummy pixels respectively further comprises a light-emitting unit, the pixel drive circuit comprises a drive transistor, the drive transistor comprises a drain electrode, and
the light-emitting unit comprises an anode and does not comprise a light-emitting layer, the drain electrode of the drive transistor is electrically connected with the anode of the light-emitting unit.

14. The display panel according to claim 13 , wherein each of the plurality of the first dummy pixels and each of the plurality of the second dummy pixels respectively further comprises:
a base substrate;
a buffer layer, provided on the base substrate;
an active layer, provided on the buffer layer;
a first insulation layer, overlaying the active layer;
the first scanning line, the second scanning line, the third scanning line, and a first gate electrode, all of which being provided in a same layer, the first scanning line, the second scanning line, the third scanning line, and the first gate electrode being provided on the first insulation layer;
a second insulation layer, overlaying the first scanning line, the second scanning line, the third scanning line, and the first gate electrode;
an initial voltage line and a second gate electrode, both of which being provided in a same layer, the initial voltage line and the second gate electrode are provided on the second insulation layer;
a third insulation layer, overlaying the initial voltage line and the second gate electrode, wherein the third insulation layer is provided with a plurality of via holes, and the plurality of via holes comprise a first via hole, a second via hole, a third via hole, a fourth via hole, a fifth via hole, a sixth via hole, and a seventh via hole; each of the first via hole, the second via hole, and the third via hole exposes the second gate electrode; each of the fifth via hole and the sixth via hole exposes the active layer; and the seventh via hole exposes the initial voltage line;
a data line, a power line, a connecting line, and the drain electrode, all of which are provided in a same layer, wherein the data line, the power line, the connecting line, the drain electrode are provided on the third insulation layer; one terminal of the drain electrode is connected with the second gate electrode through the first via hole, the other terminal of the drain electrode is connected with the active layer through the fifth via hole; the data line is connected with the active layer through the fourth via hole; the power line is connected with the second gate electrode through the second via hole and the third via hole; one terminal of the connecting line is connected with the active layer through the sixth via hole, and the other terminal of the connecting line is connected with the initial voltage line through the seventh via hole;
a fourth insulation layer, overlaying the data line, the power line, the connecting line, and the drain electrode, the fourth insulation layer being provided with an eighth via hole, the eighth via hole exposing the drain electrode;
a pixel defining layer, provided on the fourth insulation layer and defining a pixel opening, the eighth via hole being located in the pixel opening; and
the anode, provided in the pixel opening and connected with the drain electrode through the eighth via hole.

15. The display panel according to claim 1 , wherein each of the plurality of the first dummy pixels and each of the p

Assignees

• Beijing Boe Technology Dev Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Hao Xueguang
• Wu Xinyin
• Qiao Yong

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/00

  Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates · CPC title

• H10K59/88 Primary

  Dummy elements, i.e. elements having non-functional features · CPC title

• G09G2300/0413

  Details of dummy pixels or dummy lines in flat panels · CPC title