Amorphous bottom electrode structure for MIM capacitors

Patent metadata

Field	Value
Publication number	US-12527014-B2
Application number	US-202418664389-A
Country	US
Kind code	B2
Filing date	May 15, 2024
Priority date	Oct 14, 2021
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

Various embodiments of the present disclosure are directed towards an amorphous bottom electrode structure (BES) for a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode, an insulator layer overlying the bottom electrode, and a top electrode overlying the insulator layer. The bottom electrode comprises a crystalline BES and the amorphous BES, and the amorphous BES overlies the crystalline BES and forms a top surface of the bottom electrode. Because the amorphous BES is amorphous, instead of crystalline, a top surface of the amorphous BES may have a small roughness compared to that of the crystalline BES. Because the amorphous BES forms the top surface of the bottom electrode, the top surface of the bottom electrode may have a small roughness compared to what it would otherwise have if the crystalline BES formed the top surface. The small roughness may improve a lifespan of the MIM capacitor.

First claim

What is claimed is:

1 . A metal-insulator-metal (MIM) capacitor comprising:
a bottom electrode; an insulator layer overlying the bottom electrode; an interfacial layer between the bottom electrode and the insulator layer; and a top electrode overlying the insulator layer; wherein the bottom electrode comprises a crystalline structure and an amorphous structure overlying the crystalline structure, and wherein hydrogen ions are at an interface at which the amorphous structure and the interfacial layer contact each other.

2 . The MIM capacitor according to claim 1 , wherein the top electrode comprises a second crystalline structure and a second amorphous structure overlying the second crystalline structure.

3 . The MIM capacitor according to claim 1 , wherein the top electrode directly contacts the insulator layer and is entirely amorphous.

4 . The MIM capacitor according to claim 1 , further comprising:
an additional interfacial layer between and directly contacting the crystalline structure and the amorphous structure, wherein the additional interfacial layer comprises native oxide of the crystalline structure.

5 . The MIM capacitor according to claim 1 , wherein the crystalline structure has a greater width than the amorphous structure.

6 . An integrated circuit (IC) comprising a metal-insulator-metal (MIM) capacitor, wherein the MIM capacitor comprises:
a bottom electrode; an insulator layer overlying the bottom electrode; a diffusion barrier layer between and directly contacting the insulator layer and the bottom electrode, wherein the diffusion barrier layer comprises a metal oxynitride and is configured to block diffusion of oxygen; and a top electrode overlying the insulator layer; wherein the bottom electrode comprises a first bottom electrode structure (BES) and a second BES overlying the first BES, wherein a top surface of the first BES has a first average roughness, and wherein a top surface of the second BES has a second average roughness less than the first average roughness.

7 . The IC according to claim 6 , wherein the bottom electrode and the diffusion barrier layer have individual top surfaces level with each other.

8 . The IC according to claim 6 , wherein the diffusion barrier layer comprises plasma-treated native oxide of the second BES.

9 . The IC according to claim 6 , further comprising:
a pad overlying the MIM capacitor; and a via extending from the pad to the top electrode, wherein the top electrode is amorphous continuously from direct contact with the insulator layer to the via.

10 . The IC according to claim 6 , wherein the top surface of the second BES has a lesser surface area than the top surface of the first BES.

11 . The IC according to claim 6 , further comprising:
a substrate; an alternating stack of wires and vias; a pad exposed from over the alternating stack; and a pad via extending from the pad to a wire of the alternating stack, wherein the pad via extends through the top electrode and the insulator layer.

12 . The MIM capacitor according to claim 6 , wherein the first BES comprises a plurality of columnar crystalline grains at the top surface of the first BES.

13 . An integrated circuit (IC) comprising a metal-insulator-metal (MIM) capacitor, wherein the MIM capacitor comprises:
a bottom electrode; a first insulator layer overlying the bottom electrode and extending along a sidewall of the bottom electrode; a middle electrode overlying the first insulator layer; a second insulator layer overlying the middle electrode and extending along a sidewall of the middle electrode, wherein the sidewall of the middle electrode faces an opposite direction as the sidewall of the bottom electrode; and a top electrode overlying the second insulator layer; wherein the middle electrode comprises a crystalline structure and an amorphous structure overlying the crystalline structure, and wherein the top electrode, the first insulator layer, and the second insulator layer have individual sidewalls vertically stacked and edge to edge to form a common sidewall facing in the opposite direction.

14 . The IC according to claim 13 , wherein the sidewall of the middle electrode overlies the bottom electrode, laterally between the sidewall of the bottom electrode and the common sidewall.

15 . The IC according to claim 13 , wherein the crystalline structure directly contacts a top surface of the first insulator layer.

16 . The IC according to claim 13 , wherein the MIM capacitor further comprises a metal oxynitride layer between and directly contacting the second insulator layer and the amorphous structure.

17 . The IC according to claim 13 , wherein the bottom electrode comprises an additional crystalline structure and an additional amorphous structure overlying the additional crystalline structure.

18 . The IC according to claim 13 , further comprising:
a pair of wires underlying and spaced from the MIM capacitor; a pair of pads overlying and spaced from the MIM capacitor; and a pair of vias extending respectively from the pair of wires respectively to the pair of pads, wherein one of the pair of vias directly contacts the middle electrode, and wherein another one of the pair of vias directly contacts the bottom electrode and the top electrode.

19 . The MIM capacitor according to claim 1 , wherein the crystalline structure and the amorphous structure are the same material and comprise a metal nitride.

20 . The MIM capacitor according to claim 1 , wherein a top surface of the amorphous structure has a first average roughness, and wherein a top surface of the top electrode has a second average roughness greater than the first average roughness.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Hsing-Lien
• Chu Jui-Lin
• Tsai Cheng-Yuan

Classifications

• H10D84/80

  characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence) · CPC title

• H10D1/696 Primary

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/692 Primary

  Electrodes · CPC title