Semiconductor device and method of forming clip bond having multiple bond line thicknesses

US12525567B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12525567-B2
Application numberUS-202117644143-A
CountryUS
Kind codeB2
Filing dateDec 14, 2021
Priority dateDec 31, 2020
Publication dateJan 13, 2026
Grant dateJan 13, 2026

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device has a leadframe and a first electrical component disposed over the leadframe. A clip bond is disposed over the first electrical component. The clip bond has a plurality of recesses each having a different depth. A first recess is proximate to a first distal end of the first electrical component, and a second recess is proximate to a second distal end of the first electrical component opposite the first distal end of the first electrical component. A depth of the first recess is different from a depth of the second recess. A third recess is over a surface of the first electrical component. A depth of the third recess is different from the depth of the first recess and the depth of the second recess. A second electrical component is disposed over the leadframe. The clip bond extends over the second electrical component.

First claim

Opening claim text (preview).

What is claimed: 1 . A semiconductor device, comprising: a leadframe; a first electrical component disposed over the leadframe; and a clip bond disposed over the first electrical component, wherein the clip bond includes a first recess proximate to a first distal end of the first electrical component and a second recess proximate to a second distal end of the first electrical component opposite the first distal end of the first electrical component, wherein a depth of the first recess in a range of 0.215-0.235 mm measured vertically from a top surface of the first electrical component to a first bottom surface of the clip bond directly above the first distal end of the first electrical component is greater than a depth of the second recess in a range of 0.170-0.190 mm measured vertically from the top surface of the first electrical component to a second bottom surface of the clip bond directly above the second distal end of the first electrical component. 2 . The semiconductor device of claim 1 , further including a second electrical component disposed over the leadframe, wherein the clip bond extends over the second electrical component. 3 . The semiconductor device of claim 1 , further including a conductive paste deposited between the clip bond and a surface of the first electrical component, wherein the conductive paste is at least partially disposed within the first recess or second recess. 4 . A semiconductor device, comprising: a leadframe; a first electrical component disposed over the leadframe; and a clip bond disposed over the first electrical component, wherein a first thickness of the clip bond in a range of 0.002-0.022 mm proximate to directly above a first distal end of the first electrical component is less than a second thickness of the clip bond in a range of 0.047-0.067 mm proximate to directly above a second distal end of the first electrical component opposite the first distal end of the first electrical component. 5 . The semiconductor device of claim 4 , wherein the clip bond includes a third thickness over a surface of the first electrical component, wherein the third thickness is different from the first thickness and second thickness. 6 . The semiconductor device of claim 5 , further including a second electrical component disposed over the leadframe, wherein the clip bond extends over the second electrical component. 7 . The semiconductor device of claim 6 , wherein the clip bond includes a fourth thickness over a surface of the second electrical component, wherein the fourth thickness is different from the first thickness and second thickness. 8 . The semiconductor device of claim 4 , further including a conductive paste deposited between the clip bond and a surface of the first electrical component. 9 . The semiconductor device of claim 4 , further including an encapsulant deposited over the clip bond and first electrical component. 10 . A method of making a semiconductor device, comprising: providing a leadframe; disposing a first electrical component over the leadframe; and disposing a clip bond over the first electrical component by forming a first recess proximate to a first distal end of the first electrical component, and forming a second recess proximate to a second distal end of the first electrical component opposite the first distal end of the first electrical component, wherein a depth of the first recess in a range of 0.215-0.235 mm measured vertically from a top surface of the first electrical component to a first bottom surface of the clip bond directly above the first distal end of the first electrical component is greater than a depth of the second recess in a range of 0.170-0.190 mm measured vertically from the top surface of the first electrical component to a second bottom surface of the clip bond directly above the second distal end of the first electrical component. 11 . The method of claim 10 , further including disposing a second electrical component disposed over the leadframe, wherein the clip bond extends over the second electrical component. 12 . The method of claim 10 , further including depositing a conductive paste between the clip bond and a surface of the first electrical component, wherein the conductive paste is at least partially disposed within the first recess or second recess. 13 . The method of claim 10 , further including depositing an encapsulant over the clip bond and first electrical component. 14 . The method of claim 11 , wherein a first thickness of the clip bond directly above the first distal end of the first electrical component is less than a second thickness of the clip bond directly above the second distal end of the first electrical component opposite the first distal end of the first electrical component. 15 . The method of claim 14 , wherein a third thickness of the clip bond directly above the first electrical component is different from the first thickness and second thickness and a fourth thickness of the clip bond directly above the second electrical component is different from the first thickness and second thickness. 16 . The semiconductor device of claim 2 , wherein a first thickness of the clip bond directly above the first distal end of the first electrical component is less than a second thickness of the clip bond directly above the second distal end of the first electrical component opposite the first distal end of the first electrical component. 17 . The semiconductor device of claim 16 , wherein a third thickness of the clip bond directly above the first electrical component is different from the first thickness and second thickness and a fourth thickness of the clip bond directly above the second electrical component is different from the first thickness and second thickness.

Assignees

Inventors

Classifications

  • Subject matter not provided for in other groups of this subclass · CPC title

  • Strap connectors, e.g. thick copper clips for grounding of power devices · CPC title

  • Dispositions of multiple connectors or interconnections · CPC title

  • between a chip and a laterally-adjacent lead frame, conducting package substrate or heat sink · CPC title

  • between laterally-adjacent chips · CPC title

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What does patent US12525567B2 cover?
A semiconductor device has a leadframe and a first electrical component disposed over the leadframe. A clip bond is disposed over the first electrical component. The clip bond has a plurality of recesses each having a different depth. A first recess is proximate to a first distal end of the first electrical component, and a second recess is proximate to a second distal end of the first electric…
Who is the assignee on this patent?
Utac Headquarters Pte Ltd
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 13 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).