Interconnect line structures with metal chalcogenide cap materials

US12525488B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12525488-B2
Application numberUS-202117560089-A
CountryUS
Kind codeB2
Filing dateDec 22, 2021
Priority dateDec 22, 2021
Publication dateJan 13, 2026
Grant dateJan 13, 2026

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  2. Abstract

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Abstract

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Integrated circuit interconnect structures including an interconnect line metallization feature subjected to one or more chalcogenation techniques to form a cap may reduce line resistance. A top portion of a bulk line material may be advantageously crystallized into a metal chalcogenide cap with exceptionally large crystal structure. Accordingly, chalcogenation of a top portion of a bulk material can lower scattering resistance of an interconnect line relative to alternatives where the bulk material is capped with an alternative material, such as an amorphous dielectric or a fine grained metallic or graphitic material.

First claim

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What is claimed is: 1 . An integrated circuit (IC) interconnect structure, comprising: a via metallization within a dielectric material; and a line metallization over, and coupled to, the via metallization, wherein the line metallization comprises: a bulk material comprising a first metal; a liner material between a bottom of the bulk material and the dielectric material and adjacent to a sidewall of the bulk material, the liner material comprising a second metal; and a cap material over the bulk material, but not over the liner material adjacent to the sidewall of the bulk material, wherein the cap material comprises a first atomic layer of predominantly the first metal in contact with a second atomic layer of predominantly a chalcogen. 2 . The IC interconnect structure of claim 1 , wherein the chalcogen comprises S or Se. 3 . The IC interconnect structure of claim 2 , wherein the first metal is Cu, and the second metal is Ta, Mo, W, Al, Ti, W or Pt. 4 . The IC interconnect structure of claim 1 , wherein the cap material has a thickness less than 6 nm and where a top surface of the cap material is substantially co-planar with a top surface of at least one of the liner or a dielectric material adjacent to the liner. 5 . The IC interconnect structure of claim 1 , wherein the cap comprises the first atomic layer of predominantly the metal between two of the second atomic layers of predominantly the chalcogen. 6 . The IC interconnect structure of claim 1 , wherein the line metallization extends a lateral length within a plane of the IC interconnect structure and the first and second atomic layers are parallel to the plane. 7 . The IC interconnect structure of claim 1 , wherein the first atomic layer is continuous over a grain length, and wherein the grain length is at least 1 μm. 8 . The IC interconnect structure of claim 1 , further comprising a diffusion barrier over the cap, wherein the diffusion barrier comprises a second dielectric material. 9 . The IC interconnect structure of claim 8 , wherein the second dielectric material comprises nitrogen and silicon. 10 . A computer platform comprising: a power supply; and an integrated circuit (IC) coupled to the power supply, wherein the IC comprises: a device layer comprising a plurality of transistors comprising one or more semiconductor materials; and a plurality of interconnect levels, the interconnect levels further comprising the IC interconnect structure of claim 1 . 11 . The computer platform of claim 10 , wherein the IC comprises a microprocessor. 12 . The computer platform of claim 10 , wherein: the chalcogen comprises S or Se; the first metal is Cu or Mo; the cap material has a thickness less than 6 nm; the cap material comprises a first atomic layer of predominantly the Cu or Mo in contact with a second atomic layer of predominantly the S or Se; the first atomic layer is continuous over a grain length of the cap material; and the grain length is at least 1 μm.

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What does patent US12525488B2 cover?
Integrated circuit interconnect structures including an interconnect line metallization feature subjected to one or more chalcogenation techniques to form a cap may reduce line resistance. A top portion of a bulk line material may be advantageously crystallized into a metal chalcogenide cap with exceptionally large crystal structure. Accordingly, chalcogenation of a top portion of a bulk materi…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H10W20/064. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 13 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).