Register configuration system, method, and electronic device

Patent metadata

Field	Value
Publication number	US-12524249-B2
Application number	US-202318568403-A
Country	US
Kind code	B2
Filing date	Sep 19, 2023
Priority date	Sep 19, 2023
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

The present disclosure provides a register configuration system, method, and electronic device. The register configuration system includes a display processing unit, memory, and a hardware automatic control unit. The display processing unit includes multiple registers. The memory includes at least one pre-stored configuration instruction, wherein the configuration instruction is configured to indicate target registers that need to be configured in the display processing unit. The hardware automatic control unit is connected to a register configuration interface of the display processing unit. The hardware automatic control unit is configured to receive a startup command and, based on the startup command, retrieve and parse the configuration instructions from the memory. After parsing the configuration instructions, the hardware automatic control unit configures the target registers in the display processing unit. The startup command includes the storage address of the configuration instructions.

First claim

What is claimed is:

1 . A register configuration system, wherein the system comprises:
a display processing unit, wherein the display processing unit comprises multiple registers; a memory, wherein the memory comprises at least one pre-stored configuration instruction, wherein the configuration instruction is configured to indicate target registers that need to be configured in the display processing unit; and a hardware automatic control unit, wherein the hardware automatic control unit is connected to a register configuration interface of the display processing unit; the hardware automatic control unit is configured to receive a startup command and, based on the startup command, retrieve and parse the configuration instruction from the memory; after parsing the configuration instruction, the hardware automatic control unit configures the target registers in the display processing unit; and the startup command comprises a storage address of the configuration instruction; and the configuration instruction comprises an instruction type, a number of target registers whose addresses are consecutive, an offset address of a first target register, an instruction text, and an instruction end flag.

2 . The register configuration system according to claim 1 , wherein the hardware automatic control unit is further connected to an interaction interface of each data path of the display processing unit and different data paths comprise different registers; and
the hardware automatic control unit is further configured to send a configuration start command representing a start of configuring the target registers to the data paths and to receive a configuration status signal fed back from the data paths; and the configuration status signal represents whether all registers comprised in the data paths have completed their configuration.

3 . The register configuration system according to claim 2 , wherein the display processing unit comprises multiple data paths; the hardware automatic control unit is further configured to record a configuration status of registers comprised in each data path based on the configuration status signal fed back by each data path; and the configuration status represents whether the registers have completed their configuration.

4 . The register configuration system according to claim 1 , wherein the register configuration system further comprises:
a central processing unit, wherein the central processing unit is connected to the hardware automatic control unit and the central processing unit is configured to send the startup command to the hardware automatic control unit.

5 . The register configuration system according to claim 4 , wherein the hardware automatic control unit is further configured to transmit its internal status to the central processing unit; and
the central processing unit determines whether the hardware automatic control unit is functioning properly based on a received status of the hardware automatic control unit; and in case of any anomalies in the hardware automatic control unit, the central processing unit sends an interrupt command to the hardware automatic control unit, wherein the interrupt command is configured to instruct the hardware automatic control unit to stop working.

6 . The register configuration system according to claim 1 , wherein the instruction text records a calculation method for an actual configuration address of each target register; and
the hardware automatic control unit is configured to parse the configuration instruction based on the instruction type, so as to obtain the number of the target registers, the offset address of the first target register, the instruction text, and the instruction end flag; according to the number of the target registers whose addresses are consecutive, the offset address of the first target register, and the calculation method provided in the instruction text, the actual configuration address for each target register is determined; and each target register is configured based on the actual configuration address of each target register.

7 . The register configuration system according to claim 6 , wherein the instruction text further records a calculation method for a total number of the target registers whose addresses are consecutive; and
the hardware automatic control unit is configured to determine the total number of the target registers whose addresses are consecutive based on the number of the target registers whose addresses are consecutive and the calculation method for the total number of the target registers; and according to the total number of the target registers whose addresses are consecutive, the offset address of the first target register, and the instruction text, an actual configuration address for each target register are determined.

8 . A register configuration method, applied to the hardware automatic control unit in the register configuration system according to claim 1 , wherein the method comprises:
receiving the startup command; obtaining and parsing the configuration instruction from the memory based on the startup command; and configuring the target registers in the display processing unit based on the parsed configuration instruction.

9 . An electronic device, comprising:
the register configuration system according to claim 1 .

Assignees

• Verisilicon Microelectronics Shanghai Co Ltd
• Verisilicon Microelectronics Chengdu Co Ltd

Inventors

• Ye Ting
• Mu Jiebin
• Zhang Huiming
• Li Jia

Classifications

• G06F3/14

  Digital output to display device {; Cooperation and interconnection of the display device with other functional units} · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F9/485

  Task life-cycle, e.g. stopping, restarting, resuming execution (G06F9/4881 takes precedence) · CPC title

• G06F9/30101

  Special purpose registers · CPC title

• G09G2360/10

  Display system comprising arrangements, such as a coprocessor, specific for motion video images · CPC title