SiGe:GAB source or drain structures with low resistivity

Patent metadata

Field	Value
Publication number	US-12520573-B2
Application number	US-202217850782-A
Country	US
Kind code	B2
Filing date	Jun 27, 2022
Priority date	Jun 27, 2022
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium, gallium and boron. The first and second source or drain structures have a resistivity less than 2E-9 Ohm cm2.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a fin having a lower fin portion and an upper fin portion; a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side; a first source or drain structure comprising an epitaxial structure embedded in the fin at the first side of the gate stack; and a second source or drain structure comprising an epitaxial structure embedded in the fin at the second side of the gate stack, each epitaxial structure of the first and second source or drain structures comprising silicon, germanium, gallium and boron, and the first and second source or drain structures having a resistivity less than 2E-9 Ohm cm 2 .

2 . The integrated circuit structure of claim 1 , wherein an atomic concentration of the boron is in the range of 1E20 atoms/cm 3 -3E21 atoms/cm 3 .

3 . The integrated circuit structure of claim 1 , wherein the first and second source or drain structures induce a uniaxial compressive strain on the fin.

4 . The integrated circuit structure of claim 1 , wherein the first and second source or drain structures are adjacent an isolation structure.

5 . The integrated circuit structure of claim 4 , wherein the first and second source or drain structures have a lower surface below an upper surface of the isolation structure.

6 . The integrated circuit structure of claim 1 , wherein the lower fin portion includes a portion of an underlying bulk single crystalline silicon substrate.

7 . The integrated circuit structure of claim 1 , further comprising:
first and second dielectric gate sidewall spacers along the first and second sides of the gate stack, respectively.

8 . The integrated circuit structure of claim 1 , further comprising:
a first conductive contact on the epitaxial structure of the first source or drain structure; and a second conductive contact on the epitaxial structure of the second source or drain structure.

9 . The integrated circuit structure of claim 8 , wherein the first and second conductive contacts are in a partial recess in the epitaxial structures of the first and second source or drain structures, respectively.

10 . An integrated circuit structure, comprising:
a fin having a lower fin portion and an upper fin portion; a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side; a first source or drain structure comprising an epitaxial structure embedded in the fin at the first side of the gate stack, the epitaxial structure comprising a lower semiconductor layer and a capping semiconductor layer; and a second source or drain structure comprising an epitaxial structure embedded in the fin at the second side of the gate stack, the epitaxial structure comprising a lower semiconductor layer and a capping semiconductor layer, the lower semiconductor layer of each of the epitaxial structures of the first and second source or drain structures comprising silicon, germanium, gallium and boron, the capping semiconductor layer of the epitaxial structure of each of the first and second source or drain structures having a germanium concentration greater than the lower semiconductor layer, and the first and second source or drain structures having a resistivity less than 2E-9 Ohm cm 2 .

11 . The integrated circuit structure of claim 10 , wherein the lower semiconductor layer of each of the epitaxial structures of the first and second source or drain structures have an atomic concentration of boron in the range of 1E20 atoms/cm 3 -3E21 atoms/cm 3 .

12 . The integrated circuit structure of claim 10 , wherein the lower semiconductor layer of each of the epitaxial structures of the first and second source or drain structures have a germanium concentration in the range of 10% to 85%.

13 . The integrated circuit structure of claim 10 , wherein the first and second source or drain structures induce a uniaxial compressive strain on the fin.

14 . The integrated circuit structure of claim 10 , wherein the capping semiconductor layer consists essentially of germanium.

15 . The integrated circuit structure of claim 10 , wherein the lower fin portion includes a portion of an underlying bulk single crystalline silicon substrate.

16 . The integrated circuit structure of claim 10 , further comprising:
first and second dielectric gate sidewall spacers along the first and second sides of the gate stack, respectively.

17 . The integrated circuit structure of claim 10 , further comprising:
a first conductive contact on the capping semiconductor layer of the first source or drain structure; and a second conductive contact on the capping semiconductor layer of the second source or drain structure.

18 . The integrated circuit structure of claim 17 , wherein the first and second conductive contacts are in a partial recess in the capping semiconductor layers of the first and second source or drain structures, respectively.

19 . An integrated circuit structure, comprising:
a fin having a lower fin portion and an upper fin portion; a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side; a first source or drain structure comprising an epitaxial structure embedded in the fin at the first side of the gate stack, the epitaxial structure comprising a lower semiconductor layer and a capping semiconductor layer; and a second source or drain structure comprising an epitaxial structure embedded in the fin at the second side of the gate stack, the epitaxial structure comprising a lower semiconductor layer and a capping semiconductor layer, the lower semiconductor layer of each of the epitaxial structures of the first and second source or drain structures comprising silicon, germanium, gallium and boron, the capping semiconductor layer of the epitaxial structure of each of the first and second source or drain structures having a germanium concentration greater than the lower semiconductor layer, and the first and second source or drain structures having a resistivity less than 2E-9 Ohm cm 2 ; a first conductive contact on the capping semiconductor layer of the first source or drain structure; a second conductive contact on the capping semiconductor layer of the second source or drain structure; a first dielectric spacer along sidewalls of the first conductive contact, wherein the capping semiconductor layer of the first source or drain structure is confined between the first dielectric spacer; and a second dielectric spacer along sidewalls of the second conductive contact, wherein the capping semiconductor layer of the second source or drain structure is confined between the second dielectric spacer.

20 . The integrated circuit structure of claim 19 , further comprising:
first and second dielectric gate sidewall spacers along the first and second sides of the gate stack, respectively.

21 . The integrated circuit structure of claim 19 , wherein the lower semiconductor layer of each of the epitaxial structures of the first and second source or drain structures have an atomic concentration of boron in the range of 1E20 atoms/cm 3 -3E21 atoms/cm 3 .

22 . The integrated circuit structure of claim 19 , wherein the lower semiconductor layer of each of the epitaxial structures of the first and second source or drain structures have a germanium concentration in the range of 10% to 85.

23 . The integrated circuit structure

Assignees

• Intel Corp

Inventors

• Nandi Debaleena
• Zigoneanu Imola
• Dewey Gilbert
• Jahagirdar Anant H
• Kennel Harold W
• Patel Pratik
• Murthy Anand S
• Choi Chi-Hing
• Kobrinsky Mauro J
• Ghani Tahir

Classifications

• H10D62/834

  further characterised by the dopants · CPC title

• H10D62/832

  being Group IV materials comprising two or more elements, e.g. SiGe · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D30/6211

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title