Semiconductor device

Patent metadata

Field	Value
Publication number	US-12520570-B2
Application number	US-202218069200-A
Country	US
Kind code	B2
Filing date	Dec 20, 2022
Priority date	Feb 17, 2022
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

Provided is a semiconductor device in which one mesa portion of two mesa portions in contact with a gate trench portion is an active mesa portion in which an emitter region of a first conductivity type having a doping concentration higher than that of a drift region is arranged in contact with the gate trench portion, the other mesa portion of two mesa portions in contact with the gate trench portion is a dummy mesa portion having no emitter region, and a dummy contact resistance which is a resistance of the dummy mesa portion and an emitter electrode is 1000 times or more as high as an active contact resistance which is a resistance of the active mesa portion and the emitter electrode.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type; an emitter electrode provided above the upper surface of the semiconductor substrate; a plurality of trench portions provided on the upper surface of the semiconductor substrate and arranged spaced from each other in an array direction; and a plurality of mesa portions sandwiched between each of the plurality of trench portions inside the semiconductor substrate, wherein the plurality of trench portions include a gate trench portion to which a gate voltage is applied, one mesa portion of two mesa portions in contact with the gate trench portion among the plurality of mesa portions is an active mesa portion in which an emitter region of the first conductivity type having a doping concentration higher than that of the drift region is arranged in contact with the gate trench portion, an other mesa portion of the two mesa portions in contact with the gate trench portion is a dummy mesa portion not having the emitter region, and a dummy contact resistance which is a resistance of the dummy mesa portion and the emitter electrode is 1000 times or more as high as an active contact resistance which is a resistance of the active mesa portion and the emitter electrode.

2 . The semiconductor device according to claim 1 , wherein the dummy contact resistance is 5000 times or more as high as the active contact resistance.

3 . The semiconductor device according to claim 1 , wherein the dummy contact resistance is 30000 times or more as high as the active contact resistance.

4 . The semiconductor device according to claim 1 , wherein the dummy contact resistance is 50000 times or more as high as the active contact resistance.

5 . The semiconductor device according to claim 1 , wherein the dummy contact resistance is 100000 times or less as high as the active contact resistance.

6 . The semiconductor device according to claim 1 , further comprising a resistance film provided between the dummy mesa portion and the emitter electrode and formed of a material having a volume resistivity higher than that of the emitter electrode.

7 . The semiconductor device according to claim 1 , wherein
The dummy mesa portion has a region of a second conductivity type exposed on the upper surface of the semiconductor substrate, and the active mesa portion has a contact region of the second conductivity type having a doping concentration higher than that of the region of the second conductivity type of the dummy mesa portion.

8 . The semiconductor device according to claim 7 , wherein
the active mesa portion has a base region of the second conductivity type provided between the drift region and the emitter region, and a doping concentration of the region of the second conductivity type of the dummy mesa portion is not more than that of the base region.

9 . The semiconductor device according to claim 1 , further comprising an interlayer dielectric film provided between the upper surface of the semiconductor substrate and the emitter electrode, wherein
the interlayer dielectric film is provided with a first contact hole configured to connect the emitter electrode and the active mesa portion and a second contact hole configured to connect the emitter electrode and the dummy mesa portion, and in a top view, a total area of the second contact hole for one of the dummy mesa portions is smaller than a total area of the first contact hole for one of the active mesa portions.

10 . The semiconductor device according to claim 1 , wherein
the active mesa portion has a trench contact provided from the upper surface of the semiconductor substrate into the semiconductor substrate and connected to the emitter electrode, and the trench contact is not provided in the dummy mesa portion.

11 . The semiconductor device according to claim 1 , wherein
the active mesa portion has a base region of a second conductivity type provided between the drift region and the emitter region, the dummy mesa portion has the base region between the drift region and the upper surface of the semiconductor substrate, the active mesa portion and the dummy mesa portion have an accumulation region of the first conductivity type having a doping concentration higher than that of the drift region between the base region and the drift region, and an integrated concentration obtained by integrating the doping concentration of the accumulation region of the dummy mesa portion in a depth direction is larger than an integrated concentration obtained by integrating the doping concentration of the accumulation region of the active mesa portion in the depth direction.

12 . The semiconductor device according to claim 1 , wherein
the gate trench portion includes a gate conductive portion and a gate dielectric film provided between the gate conductive portion and the semiconductor substrate, and the gate dielectric film in contact with the dummy mesa portion is thinner than the gate dielectric film in contact with the active mesa portion.

13 . The semiconductor device according to claim 1 , wherein
the plurality of trench portions include a dummy trench portion which is arranged adjacent to the gate trench portion with the dummy mesa portion sandwiched therebetween in the array direction and is applied with a voltage different from the gate voltage, among the mesa portions in contact with the dummy trench portion, the mesa portion on a side of the gate trench portion is a first one of the dummy mesa portions not having the emitter region, and the mesa portion on a side opposite to the gate trench portion is a second one of the dummy mesa portions not having the emitter region, and the dummy contact resistance of the first one of the dummy mesa portions is lower than the dummy contact resistance of the second one of the dummy mesa portions.

14 . The semiconductor device according to claim 1 , wherein
the plurality of mesa portions has a third one of the dummy mesa portions not having the emitter region, and a fourth one of the dummy mesa portions arranged closer to an end portion of the semiconductor substrate than the third one of the dummy mesa portions in the array direction and not having the emitter region, and the dummy contact resistance of the fourth one of the dummy mesa portions is lower than the dummy contact resistance of the third one of the dummy mesa portions.

15 . The semiconductor device according to claim 1 , further comprising a wiring connected to a connection region on an upper surface of the emitter electrode, wherein
the plurality of mesa portions include a fifth one of the dummy mesa portions overlapping with the connection region in a top view and not having the emitter region, and a sixth one of the dummy mesa portions not overlapping with the connection region in the top view and not having the emitter region, and the dummy contact resistance of the fifth one of the dummy mesa portions is lower than the dummy contact resistance of the sixth one of the dummy mesa portions.

16 . The semiconductor device according to claim 1 , wherein
a current-voltage change rate characteristic indicating a relationship between a collector current flowing through the semiconductor device and a voltage change rate of a collector-emitter voltage when the semiconductor device is turned on includes:
a peak portion in which the voltage change rate exhibits a local maximum value; and
a maintaining and increasing region in which t

Assignees

• Fuji Electric Co Ltd

Inventors

• Sakurai Yosuke
• Yamano Akio
• Noguchi Seiji
• Hamasaki Ryutaro
• Yamada Takuya
• Ozaki Daisuke

Classifications

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title

• H10D12/481 Primary

  having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs · CPC title

• H10D8/422

  PN diodes having the PN junctions in mesas · CPC title

• H10D64/232

  Emitter electrodes for IGBTs · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title