Semiconductor devices with modified source/drain feature and methods thereof

Patent metadata

Field	Value
Publication number	US-12520526-B2
Application number	US-202418767291-A
Country	US
Kind code	B2
Filing date	Jul 9, 2024
Priority date	Mar 5, 2021
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

A semiconductor structure includes semiconductor layers vertically stacked above a substrate, a gate structure wrapping around each of the semiconductor layers, a gate spacer disposed on sidewalls of the gate structure, a source/drain (S/D) feature abutting the semiconductor layers, and an S/D contact landing on a top surface of the S/D feature. In a cross-sectional view along a lengthwise direction of the semiconductor layers, a topmost point of the top surface of the S/D feature is above a top surface of a topmost one of the semiconductor layers, and a bottommost point of the top surface of the S/D feature is below the top surface of the topmost one of the semiconductor layers.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a plurality of semiconductor layers vertically stacked above a substrate; a gate structure wrapping around each of the semiconductor layers; a gate spacer disposed on sidewalls of the gate structure; a source/drain (S/D) feature abutting the semiconductor layers; an S/D contact landing on a top surface of the S/D feature; and a dielectric layer disposed on a sidewall of the gate spacer, wherein in a cross-sectional view along a lengthwise direction of the semiconductor layers, a topmost point of the top surface of the S/D feature is above a top surface of a topmost one of the semiconductor layers, a bottommost point of the top surface of the S/D feature is below the top surface of the topmost one of the semiconductor layers, the S/D feature includes a first layer and a second layer underneath the first layer, the second layer differs from the first layer in composition, and the dielectric layer interfaces both the first layer and the second layer of the S/D feature.

2 . The semiconductor structure of claim 1 , wherein a bottommost portion of the S/D contact is below the top surface of the topmost one of the semiconductor layers.

3 . The semiconductor structure of claim 1 , wherein a middle portion of the top surface of the S/D feature protrudes upwardly into the S/D contact.

4 . The semiconductor structure of claim 1 , wherein a middle portion of the top surface of the S/D feature has a concave shape.

5 . The semiconductor structure of claim 4 , wherein the topmost point of the top surface of the S/D feature is located at an edge of the concave shape.

6 . The semiconductor structure of claim 1 , wherein the first layer contours a bottom surface of the S/D contact and the second layer is disposed over ends of the semiconductor layers.

7 . The semiconductor structure of claim 6 , further comprising:
inner spacers disposed between the S/D feature and the gate structure, wherein the first layer is in physical contact with the inner spacers.

8 . The semiconductor structure of claim 6 , wherein the dielectric layer includes a contact etch stop layer disposed on the S/D feature and an inter-layer dielectric layer disposed on the contact etch stop layer.

9 . The semiconductor structure of claim 6 , wherein the second layer extends continuously from a sidewall of a bottommost one of the semiconductor layers to a top surface of the substrate.

10 . The semiconductor structure of claim 1 , wherein the topmost point of the top surface of the S/D feature is above the top surface of the topmost one of the semiconductor layers for 1 nm to 5 nm.

11 . A semiconductor structure, comprising:
a first transistor, the first transistor comprising:
a plurality of first semiconductor layers vertically stacked above a substrate;
a first gate structure wrapping around each of the first semiconductor layers;
a first gate spacer disposed on sidewalls of the first gate structures; and
a first source/drain (S/D) feature abutting the first semiconductor layers; and
a second transistor, the second transistor comprising:
a plurality of second semiconductor layers vertically stacked above the substrate;
a second gate structure wrapping around each of the second semiconductor layers;
a second gate spacer disposed on sidewalls of the second gate structure; and
a second S/D feature abutting the second semiconductor layers,
wherein in a cross-sectional view along a lengthwise direction of the first and second semiconductor layers, the first S/D feature is narrower and taller than the second S/D feature.

12 . The semiconductor structure of claim 11 , wherein the first S/D feature includes a first epitaxial layer and a second epitaxial layer disposed on the first epitaxial layer, the first epitaxial layer includes a dopant concentration less than the second epitaxial layer, and the second epitaxial layer partially covers a top surface of the first epitaxial layer.

13 . The semiconductor structure of claim 12 , wherein the second epitaxial layer is free of contact with the first gate spacer.

14 . The semiconductor structure of claim 12 , wherein the second S/D feature includes a third epitaxial layer and a fourth epitaxial layer disposed on the third epitaxial layer, the third epitaxial layer includes a dopant concentration less than the fourth epitaxial layer, and the fourth epitaxial layer fully covers a top surface of the third epitaxial layer.

15 . The semiconductor structure of claim 14 , wherein the fourth epitaxial layer is in physical contact with the second gate spacer.

16 . The semiconductor structure of claim 11 , further comprising:
a plurality of third semiconductor layers vertically stacked above the substrate, wherein the third semiconductor layers are sandwiched between and in physical contact with the first and second S/D features.

17 . A semiconductor structure, comprising:
a first gate structure engaging a first channel region, the first gate structure including a first sidewall; a second gate structure engaging a second channel region, the second gate structure including a second sidewall opposing the first sidewall; a first gate spacer disposed on the first sidewall of the first gate structure; a second gate spacer disposed on the second sidewall of the second gate structure; a source/drain (S/D) feature sandwiched between the first and second channel regions; and a dielectric layer disposed on sidewalls of the first and second gate spacers, wherein a topmost portion of the S/D feature is above top surfaces of the first and second channel regions, wherein the S/D feature includes a first epitaxial layer and a second epitaxial layer disposed on the first epitaxial layer, the first epitaxial layer includes a dopant concentration less than the second epitaxial layer, and the second epitaxial layer is free of contact with either of the first and second gate spacers, and wherein the dielectric layer interfaces both the first epitaxial layer and the second epitaxial layer.

18 . The semiconductor structure of claim 17 , wherein a middle point of a top surface of the S/D feature is below the top surfaces of the first and second channel regions.

19 . The semiconductor structure of claim 17 , wherein a top surface of the S/D feature includes a convex shape with an edge point of the convex shape below the top surfaces of the first and second channel regions.

20 . The semiconductor structure of claim 17 , further comprising:
a S/D contact landing on a top surface of the S/D feature, wherein a bottommost portion of the S/D contact is below the top surfaces of the first and second channel regions.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lai Wei-Jen
• Lee Wei-Yang
• Chen De-Fang
• Shih Ting-Wen

Classifications

• H10P14/6319

  Formation by plasma treatments, e.g. plasma oxidation of the substrate · CPC title

• H10P14/3452

  Microstructure · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D64/01

  Manufacture or treatment · CPC title