Method and apparatus improving gate oxide reliability by controlling accumulated charge

Patent metadata

Field	Value
Publication number	US-12520525-B2
Application number	US-202418439664-A
Country	US
Kind code	B2
Filing date	Feb 12, 2024
Priority date	Jul 11, 2005
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

A method and apparatus are disclosed for use in improving gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit includes a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge. Determinations are made of effects of an uncontrolled accumulated charge and a controlled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the determinations, and the circuit is operated using techniques for ACC operatively coupled to the SOI MOSFET. In one embodiment, the ACC techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

First claim

What is claimed is:

1 . A system comprising:
a first port; a second port; a third port; a switch configured to selectively provide a signal received at the first port to the second port or the third port based on a first switch control signal and a second switch control signal, wherein the switch comprises:
a first transistor coupled between the first port and the second port and configured to be in an on state or an off state based on the first switch control signal, wherein the switch is configured to provide the signal received at the first port to the second port via at least the first transistor; and
a second transistor coupled between the first port and the third port and configured to be in an on state or an off state based on the second switch control signal, wherein the switch is configured to provide the signal received at the first port to the third port via at least the second transistor; and
a first accumulated charge sink (ACS) coupled to the first transistor and configured to receive a first bias signal during at least a portion of a duration when the first transistor is in the off state to prevent charge from accumulating in a body of the first transistor.

2 . The system of claim 1 , wherein the signal is a radio frequency (RF) signal, wherein the switch is configured to provide the signal received at the first port to the second port via at least the first transistor when the first transistor is in the on state and the second transistor is in the off state.

3 . The system of claim 1 , wherein the switch is configured to provide the signal received at the first port to the third port via at least the second transistor when the first transistor is in the off state and the second transistor is in the on state.

4 . The system of claim 1 , further comprising a second ACS coupled to the second transistor and configured to receive a second bias signal during at least a portion of a duration when the second transistor is in the off state to prevent charge from accumulating in a body of the second transistor, and wherein the first port is an input port of the system, the second port is an output port of the system, and the third port is connected to ground.

5 . The system of claim 1 , wherein the first ACS is coupled to a gate and the body of the first transistor.

6 . The system of claim 1 , wherein the first bias signal has a voltage level equal to or more negative than a voltage level of a bias signal applied to a source of the first transistor and a voltage level of a bias signal applied to a drain of the first transistor.

7 . The system of claim 1 , wherein, during the portion of the duration, the first transistor is configured to be electrically biased to have a voltage level substantially more negative than a lowest voltage level of the following: ground, a voltage level associated with a source of the first transistor, and a voltage level associated with a drain of the first transistor.

8 . The system of claim 1 , further comprising a semiconductor-on-insulator substrate, wherein the switch is formed in a layer of semiconductor material.

9 . The system of claim 1 , wherein the switch further comprises at least one additional transistor, wherein the first transistor and the at least one additional transistor are coupled together in a stacked configuration, and wherein the stacked configuration is coupled between the first port and the second port.

10 . The system of claim 1 , wherein the switch further comprises at least one additional transistor, and wherein the second transistor and the at least one additional transistor are coupled together in a stacked configuration.

11 . The system of claim 1 , further comprising a diode coupled between the first ACS and a gate of the first transistor.

12 . A method comprising:
selectively providing a signal received at a first port to a second port or a third port based on a first switch control signal and a second switch control signal, wherein the selectively providing comprises:
selectively providing the signal received at the first port to the second port via at least a first transistor, wherein the first transistor is coupled between the first port and the second port and is in an on state or an off state based on the first switch control signal; and
selectively providing the signal received at the first port to the third port via at least a second transistor, wherein the second transistor is coupled between the first port and the third port and is in an on state or an off state based on the second switch control signal; and
receiving, by a first accumulated charge sink (ACS) coupled to the first transistor, a first bias signal during at least a portion of a duration when the first transistor is in the off state to prevent charge from accumulating in a body of the first transistor.

13 . The method of claim 12 , wherein the selectively providing the signal received at the first port to the second port comprises selectively providing the signal received at the first port to the second port via the first transistor and at least one additional transistor, and wherein the charge is associated with carriers having a polarity opposite a polarity of carriers associated with a source of the first transistor and a drain of the first transistor.

14 . The method of claim 12 , further comprising receiving, by a second ACS coupled to the second transistor, a second bias signal during at least a portion of a duration when the second transistor is in the off state to prevent charge from accumulating in a body of the second transistor, wherein the first port is an input port, the second port is an output port, and the third port is connected to ground.

15 . The method of claim 12 , further comprising preventing current flow into the body of the first transistor when the first transistor is in the on state.

16 . The method of claim 12 , wherein the signal is a radio frequency (RF) signal.

17 . A system comprising:
means for selectively providing a signal received at a first port to a second port or a third port based on a first switch control signal and a second switch control signal received by the means for selectively providing, wherein the means for selectively providing the signal comprises:
means for selectively providing the signal received at the first port to the second port based on the first switch control signal; and
means for selectively providing the signal received at the first port to the third port based on the second switch control signal; and
means for accumulated charge sinking to prevent charge from accumulating in a first portion of the means for selectively providing the signal received at the first port to the second port based on a first bias signal received during at least a portion of a duration when the first portion is associated with an off state.

18 . The system of claim 17 , further comprising means for accumulated charge sinking to prevent charge from accumulating in a second portion of the means for selectively providing the signal received at the first port to the third port based on a second bias signal received during at least a portion of a duration when the second portion is associated with an off state.

19 . The system of claim 17 , further comprising means for preventing current flow into the first portion when the first portion is associated with the on state.

20 . The system of claim 17 , wherein the signal is a radio frequency (RF) signal.

Assignees

• Psemi Corp

Inventors

• Stuber Michael A
• Brindle Christopher N
• Kelly Dylan J
• Kemerling Clint L
• Imthurn George P
• Welstand Robert B
• Burgener Mark L
• Dribinsky Alexander
• Kim Tae-Youn

Classifications

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10D30/6759

  Silicon-on-sapphire [SOS] substrates · CPC title

• H10D30/6744

  Monocrystalline silicon · CPC title

• H10D30/6743

  Silicon · CPC title

• H10D30/6739

  Conductor-insulator-semiconductor electrodes · CPC title