Semiconductor device and method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-12520491-B2
Application number	US-202418586866-A
Country	US
Kind code	B2
Filing date	Feb 26, 2024
Priority date	Jun 16, 2017
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first conductor over a substrate; a second conductor comprising an opening over the first conductor; and an oxide semiconductor embedded in the opening in the second conductor, wherein the oxide semiconductor comprises a first region extending in a first direction perpendicular or substantially perpendicular to a top surface of the substrate and a second region extending in a second direction parallel or substantially parallel to the top surface of the substrate, and wherein the second region of the oxide semiconductor is electrically connected to the first conductor.

2 . The semiconductor device according to claim 1 ,
wherein the oxide semiconductor comprises In, an element M, and Zn, and wherein the element M is Al, Ga, Y, or Sn.

3 . The semiconductor device according to claim 1 ,
wherein the oxide semiconductor comprises a first layer and a second layer in contact with an inner wall of the first layer, and wherein an energy gap of the second layer is narrower than an energy gap of the first layer.

4 . The semiconductor device according to claim 1 ,
wherein the first conductor is one of a bit line and a source line, and wherein the second conductor serves as a gate of a transistor.

5 . The semiconductor device according to claim 1 , wherein the first region of the oxide semiconductor comprises a first low-resistance region and a second low-resistance region with a channel formation region of a transistor therebetween.

6 . The semiconductor device according to claim 5 , wherein each of the first low-resistance region and the second low-resistance region is in contact with a layer containing at least one of a metal element, hydrogen, and nitrogen.

7 . A semiconductor device comprising:
a first conductor and a second conductor over a substrate; a third conductor comprising a first opening over the first conductor and a second opening over the second conductor; a first oxide semiconductor embedded in the first opening in the third conductor; and a second oxide semiconductor embedded in the second opening in the third conductor, wherein each of the first oxide semiconductor and the second oxide semiconductor comprises a first region extending in a first direction perpendicular or substantially perpendicular to a top surface of the substrate and a second region extending in a second direction parallel or substantially parallel to the top surface of the substrate, wherein the second region of the first oxide semiconductor is electrically connected to the first conductor, wherein the first oxide semiconductor comprises a channel formation region of a first transistor, wherein the second oxide semiconductor comprises a channel formation region of a second transistor, and wherein the second transistor is adjacent to the first transistor in the second direction.

8 . The semiconductor device according to claim 7 ,
wherein each of the first oxide semiconductor and the second oxide semiconductor comprises In, an element M, and Zn, and wherein the element M is Al, Ga, Y, or Sn.

9 . The semiconductor device according to claim 7 ,
wherein each of the first oxide semiconductor and the second oxide semiconductor comprises a first layer and a second layer in contact with an inner wall of the first layer, and wherein an energy gap of the second layer is narrower than an energy gap of the first layer.

10 . The semiconductor device according to claim 7 ,
wherein each of the first conductor and the second conductor is one of a bit line and a source line, and wherein the third conductor serves as a gate of the first transistor and a gate of the second transistor.

11 . The semiconductor device according to claim 7 , wherein the first region of the first oxide semiconductor comprises a first low-resistance region and a second low-resistance region with the channel formation region of the first transistor therebetween.

12 . The semiconductor device according to claim 11 , wherein each of the first low-resistance region and the second low-resistance region is in contact with a layer containing at least one of a metal element, hydrogen, and nitrogen.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Kimura Hajime
• Matsuzaki Takanori
• Kato Kiyoshi
• Okamoto Satoru

Classifications

• H10D64/685

  being perpendicular to the channel plane · CPC title

• H10D62/80

  characterised by the materials · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title