Semiconductor package

Patent metadata

Field	Value
Publication number	US-12519048-B2
Application number	US-202318212939-A
Country	US
Kind code	B2
Filing date	Jun 22, 2023
Priority date	Sep 30, 2022
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

A semiconductor package includes: a first redistribution structure including at least one first redistribution layer and at least one first insulating layer; a first semiconductor chip electrically connected to the at least one first redistribution layer and disposed on a first surface of the first redistribution structure; a second semiconductor chip disposed on an upper surface of the first semiconductor chip; a first encapsulant disposed on a second surface of the first redistribution structure opposite the first surface of the first redistribution layer; first conductive posts electrically connected to the first semiconductor chip and penetrating the first encapsulant; and under bump metallurgy (UBM) structures disposed on a lower surface of the first encapsulant, wherein at least a portion of the UBM structures overlap at least a portion of the first conductive posts in a penetration direction of the first conductive posts and are connected to the first conductive posts.

First claim

What is claimed is:

1 . A semiconductor package, comprising:
a first redistribution structure comprising at least one first redistribution layer and at least one first insulating layer; a first semiconductor chip electrically connected to the at least one first redistribution layer and disposed on a first surface of the first redistribution structure; a second semiconductor chip on an upper surface of the first semiconductor chip; a first encapsulant on a second surface of the first redistribution structure opposite the first surface of the first redistribution layer; first conductive posts electrically connected to the first semiconductor chip and penetrating the first encapsulant; and under bump metallurgy (UBM) structures on a lower surface of the first encapsulant, wherein at least a portion of the UBM structures overlap at least a portion of the first conductive posts in a penetration direction of the first conductive posts, and are connected to the first conductive posts.

2 . The semiconductor package of claim 1 , further comprising:
first bumps, between the first semiconductor chip and the first redistribution structure, connecting the first semiconductor chip to first redistribution structure, wherein the first semiconductor chip comprises a through via electrically connecting the second semiconductor chip to the at least one first redistribution layer.

3 . The semiconductor package of claim 1 , further comprising:
an impedance element encapsulated by the first encapsulant, spaced apart from the first conductive posts, and overlapping the first semiconductor chip in a penetration direction of the first conductive posts; and terminal structures, between the impedance element and the first redistribution structure, connecting the impedance element to the first redistribution structure.

4 . The semiconductor package of claim 1 ,
wherein a maximum width of each of the UBM structures is greater than a maximum width of each of the first conductive posts, and wherein a thickness of each of the UBM structures is greater than a thickness of each of the at least one first redistribution layer.

5 . The semiconductor package of claim 1 , further comprising:
a second encapsulant encapsulating the first semiconductor chip; and a second conductive post penetrating the second encapsulant.

6 . The semiconductor package of claim 1 , further comprising:
a second redistribution structure, on a lower surface of the first encapsulant, providing a dispositional region for the UBM structures, and comprising at least one second redistribution layer and at least one second insulating layer.

7 . The semiconductor package of claim 6 , wherein at least a portion of the UBM structures is in the at least one second insulating layer, and extend to at least a portion of the first conductive posts.

8 . The semiconductor package of claim 6 ,
wherein one of the at least one second redistribution layer is disposed around the UBM structures, and wherein a number of the at least one first redistribution layer is greater than a number of the at least one second redistribution layer.

9 . The semiconductor package of claim 6 , wherein each of the UBM structures comprises:
a first UBM layer surrounded by the at least one second insulating layer; and a second UBM layer, between the at least one second insulating layer and the first UBM layer, comprising a material different from a metal material of the first UBM layer.

10 . The semiconductor package of claim 6 , wherein the UBM structures comprise:
first UBM structures overlapping a portion of the first conductive posts in a penetration direction of the first conductive posts, and connected to the first conductive posts; and second UBM structures, not overlapping the first conductive posts in a direction in which the first redistribution structure and the second redistribution structure oppose each other.

11 . The semiconductor package of claim 10 , wherein a two-dimensional arrangement coherence of the second UBM structures is higher than a two-dimensional arrangement coherence of the first UBM structures.

12 . A semiconductor package, comprising:
a first redistribution structure comprising at least one first redistribution layer and at least one first insulating layer; a first semiconductor chip electrically connected to the at least one first redistribution layer and disposed on a first surface of the first redistribution structure; a second redistribution structure, on a second surface of the first redistribution structure, opposite the first surface of the first redistribution layer, and comprising at least one second redistribution layer and at least one second insulating layer; a first encapsulant between the first and second redistribution structures; an impedance element encapsulated by the first encapsulant; terminal structures connecting the impedance element to the first redistribution structure; first conductive posts electrically connected to the first semiconductor chip, penetrating through the first encapsulant and bypassing the impedance element; and under bump metallurgy (UBM) structures electrically connected to the first conductive posts and disposed on the second redistribution structure, wherein at least a portion of the UBM structures overlap the impedance element in a direction in which the first redistribution structure and the second redistribution structure oppose each other.

13 . The semiconductor package of claim 12 , further comprising:
a second semiconductor chip on an upper surface opposite the first semiconductor chip; wherein the first semiconductor chip comprises a through via electrically connecting the second semiconductor chip to the at least one first redistribution layer.

14 . The semiconductor package of claim 13 ,
wherein a maximum width of each of the UBM structures is greater than a maximum width of each of the first conductive posts, and wherein a thickness of each of the UBM structures is greater than a thickness of each of the at least one first redistribution layer.

15 . The semiconductor package of claim 14 ,
wherein the impedance element comprises a capacitor overlapping the first semiconductor chip in a penetration direction of the first conductive posts, and wherein the UBM structures comprises:
first UBM structures overlapping a portion of the first conductive posts in a penetration direction of the first conductive posts and connected to the first conductive posts; and
second UBM structures overlapping the impedance element in a direction in which the first redistribution structure and the second redistribution structure oppose each other.

16 . The semiconductor package of claim 15 ,
wherein the first UBM structures are disposed in the at least one second insulating layer and extend to at least a portion of the first conductive posts, and wherein the second UBM structures are disposed in the at least one second insulating layer.

17 . The semiconductor package of claim 16 ,
wherein a number of the at least one first redistribution layer is greater than a number of the at least one second redistribution layer, and wherein one of the at least one second redistribution layer is around the UBM structures.

18 . The semiconductor package of claim 17 , wherein each of the UBM structures comprises:
a first UBM layer surrounded by the at least one second insulating layer; and a second UBM layer, between the at least one second insulating layer and the first UBM layer, comprising a material

Assignees

• Samsung Electronics Co Ltd

Inventors

• Suk Kyounglim
• Kim Jihwang
• Lee Suchang
• Hwang Hyeonjeong

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title