Semiconductor device and method of making

Patent metadata

Field	Value
Publication number	US-12519035-B2
Application number	US-202117466417-A
Country	US
Kind code	B2
Filing date	Sep 3, 2021
Priority date	Jul 8, 2021
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

A semiconductor device includes a substrate, a first cell having a first functionality, and a second cell having a second functionality. The first cell includes a first portion on a first side of the substrate, wherein the first portion includes a first conductive element; a second portion on a second side of the substrate, wherein the second portion includes a second conductive element; and a first conductive via extending through the substrate and electrically connecting the first conductive element to the second conductive element. The second cell includes a third portion on the first side of the substrate, wherein the third portion includes a third conductive element; a fourth portion on the second side of the substrate, wherein the fourth portion includes a fourth conductive element; and a second conductive via extending through the substrate and electrically connecting the third conductive element to the fourth conductive element.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a semiconductor substrate; a first cell, wherein the first cell has a first functionality, and the first cell comprises:
a first portion on a first side of the semiconductor substrate, wherein the first portion comprises a first conductive element, and the first conductive element comprises a gate electrode or a source/drain electrode;
a second portion on a second side of the semiconductor substrate opposite the first side, wherein the second portion comprises a second conductive element; and
a first conductive via extending through the semiconductor substrate, wherein the first conductive via electrically connects the first conductive element to the second conductive element; and
a second cell, wherein the second cell has a second functionality, and the second cell comprises:
a third portion on the first side of the semiconductor substrate, wherein the third portion comprises a third conductive element;
a fourth portion on the second side of the semiconductor substrate, wherein the fourth portion comprises a fourth conductive element; and
a second conductive via extending through the semiconductor substrate, wherein the second conductive via electrically connects the third conductive element to the fourth conductive element.

2 . The semiconductor device of claim 1 , wherein the first cell has a first layout type, and the second cell has a second layout type.

3 . The semiconductor device of claim 1 , wherein the first portion has a first layout type, and the second portion has a second layout type.

4 . The semiconductor device of claim 1 , wherein the first cell is a horizontal stacked cell, including two signal lines, and having a first channel width, and the second cell is vertical mirrored, includes 4 signal lines, and has a small second channel width less than the first channel width.

5 . The semiconductor device of claim 1 , further comprising a third cell, wherein the third cell comprises:
a fifth portion on the first side of the semiconductor substrate, wherein the fifth portion comprises a fifth conductive element; a sixth portion on the second side of the semiconductor substrate, wherein the sixth portion comprises a sixth conductive element; and a third conductive via extending through the semiconductor substrate, wherein the third conductive via electrically connects the fifth conductive element to the sixth conductive element.

6 . The semiconductor device of claim 5 , wherein the first cell has a first layout type, the second cell has a second layout type, the third cell has a third layout type, and the third layout type is different from at least one of the first layout type or the second layout type.

7 . The semiconductor device of claim 6 , wherein the first cell is spaced from the second cell in a first direction, the first cell is spaced from the third cell in a second direction perpendicular to the first direction, and the third layout type is different from the first layout type.

8 . The semiconductor device of claim 6 , wherein the second cell is spaced from the first cell in a first direction, the second cell is spaced from the third cell in a second direction perpendicular to the first direction, and the third layout type is different from the second layout type.

9 . The semiconductor device of claim 1 , wherein the first conductive element includes a first source/drain (S/D) electrode, and the second conductive element includes a second S/D electrode.

10 . The semiconductor device of claim 1 , wherein the first conductive element includes a first gate electrode, and the second conductive element includes a second gate electrode.

11 . A semiconductor device comprising:
a semiconductor substrate; a first cell, wherein the first cell has a first threshold voltage, and the first cell comprises:
a first conductive element on a first side of the semiconductor substrate;
a second conductive element on a second side of the semiconductor substrate opposite the first side; and
a first conductive via extending through the semiconductor substrate, wherein the first conductive via electrically connects the first conductive element to the second conductive element; and
a second cell, wherein the second cell has a second threshold voltage, and the second cell comprises:
a third conductive element on the first side of the semiconductor substrate;
a fourth conductive element on the second side of the semiconductor substrate; and
a second conductive via extending through the semiconductor substrate, wherein the second conductive via electrically connects the third conductive element to the fourth conductive element.

12 . The semiconductor device of claim 11 , wherein the first conductive element comprises a gate electrode.

13 . The semiconductor device of claim 11 , wherein the first conductive element comprises a source/drain electrode.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lai Chih-Yu
• Chen Chih-Liang
• Lu Chi-Yu
• Chiu Shang-Hsuan

Classifications

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W20/427

  Power or ground buses · CPC title