Level shifter for display device reducing number of data bits for specifying an output channel and display device including the same

Patent metadata

Field	Value
Publication number	US-12518690-B2
Application number	US-202418917858-A
Country	US
Kind code	B2
Filing date	Oct 16, 2024
Priority date	Nov 8, 2023
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

Provided is a display device including a display panel configured to display an image, a scan driver configured to supply a scan signal to the display panel, a level shifter configured to generate gate control signals to drive the scan driver, a power supply configured to supply a voltage to the level shifter, and a timing controller configured to control the level shifter. The level shifter includes a level shifter output setting circuit implemented, so that at least one output channel is selected based on transmission signals supplied from the timing controller and an output state of the selected output channel is selected as a high voltage or a low voltage.

First claim

What is claimed is:

1 . A display device comprising:
a display panel configured to display an image; a scan driver configured to supply a scan signal to the display panel; a level shifter configured to generate gate control signals to drive the scan driver; a power supply configured to supply a voltage to the level shifter; and a timing controller configured to control the level shifter, wherein the level shifter comprises a level shifter output setting circuit implemented so that at least one output channel is selected based on transmission signals supplied from the timing controller and an output state of the selected output channel is selected as a high voltage or a low voltage, and wherein the level shifter output setting circuit comprises:
a state value setter configured to set an output state of the selected output channel based on a first part of the transmission signals;
a state value storage configured to temporarily store a state value in the state value setter based on a second part of the transmission signals in a storage prepared therein;
a driving circuit configured to generate a driving signal based on the state value stored in the state value storage; and
an output circuit configured to operate based on the driving signal generated from the driving circuit and output the high voltage or the low voltage based on a gate high voltage and a gate low voltage supplied from the power supply.

2 . The display device according to claim 1 , wherein the level shifter output setting circuit selects the at least one output channel in response to a first bit value included in the transmission signals, and selects an output state of the selected output channel in response to a second bit value included in the transmission signals as the high voltage or the low voltage.

3 . The display device according to claim 2 , wherein the level shifter output setting circuit modulates a level of the high voltage or the low voltage in response to a third bit value included in the transmission signals.

4 . The display device according to claim 1 , wherein the state value setter comprises:
state value setting switches configured to be turned on in response to a channel selection signal among the transmission signals; and state value setting capacitors configured to store a high state value or a low state value in response to a channel state setting signal among the transmission signals.

5 . The display device according to claim 4 , wherein the state value storage comprises:
first state value storage switches configured to be turned on in response to a first control signal among the transmission signals; first state value storage capacitors configured to store state values stored in the state value setting capacitors in response to switching operations of the first state value storage switches; second state value storage switches configured to be turned on in response to a second control signal among the transmission signals; and second state value storage capacitors configured to latch the state values stored in the first state value storage capacitors in response to switching operations of the second state value storage switches.

6 . A level shifter comprising:
a reception circuit configured to receive transmission signals transmitted from an exterior; and a level shifter output setting circuit implemented so that at least one output channel is selected based on the transmission signals and an output state of the selected output channel is selected as a high voltage or a low voltage, and wherein the level shifter output setting circuit comprises:
a state value setter configured to set an output state of the selected output channel based on a first part of the transmission signals;
a state value storage configured to temporarily store a state value in the state value setter based on a second part of the transmission signals in a storage prepared therein;
a driving circuit configured to generate a driving signal based on the state value stored in the state value storage; and
an output circuit configured to operate based on the driving signal generated from the driving circuit and output the high voltage or the low voltage based on a gate high voltage and a gate low voltage supplied from the exterior.

7 . The level shifter according to claim 6 , wherein the level shifter output setting circuit selects the at least one output channel in response to a first bit value included in the transmission signals, and selects an output state of the selected output channel in response to a second bit value included in the transmission signals as the high voltage or the low voltage.

8 . The level shifter according to claim 7 , wherein the level shifter output setting circuit modulates a level of the high voltage or the low voltage in response to a third bit value included in the transmission signals.

Assignees

• Lg Display Co Ltd

Inventors

• Kim Jung Jae
• Lee Sang Uk
• Han Jae Won
• Park Min Gyu

Classifications

• G09G2310/0289

  Details of voltage level shifters arranged for use in a driving circuit · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G2230/00

  Details of flat display driving waveforms · CPC title