Level shifter and display device including the same

Patent metadata

Field	Value
Publication number	US-12374266-B2
Application number	US-202318528481-A
Country	US
Kind code	B2
Filing date	Dec 4, 2023
Priority date	Dec 28, 2022
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

Embodiments disclose a level shifter including a logic unit configured to receive timing data and channel data and output an edge signal and a channel signal at a time point defined in the timing data, and a channel selection unit configured to select at least one channel from among a plurality of connected channels according to the channel signal and transmit the edge signal, and a display device including the same.

First claim

What is claimed is:

1. A level shifter comprising:
at least one input terminal;
a plurality of output terminals;
a logic circuit configured to receive timing data defining a time point and channel data via the at least one input terminal, and output an edge signal at the time point defined in the timing data and a channel signal based on the channel data; and
a channel selection circuit connected to the logic circuit and including a plurality of channels that each correspond to one of the plurality of output terminals, the channel selection circuit configured to receive the edge signal and the channel signal, select a channel from the plurality of channels according to the channel signal, and output the edge signal to the selected channel,
wherein a gate control signal that is based on the edge signal is output by the level shifter to a gate driving circuit that is connected to the level shifter via an output terminal from the plurality of output terminals that corresponds to the selected channel.

2. The level shifter of claim 1 , wherein the timing data includes rising data and falling data, and the channel data includes rising channel data that specifies the channel from the plurality of channels to which a rising edge is to be input and falling channel data that specifies a channel from the plurality of channels to which a falling edge is to be input.

3. The level shifter of claim 2 , wherein the logic circuit comprises:
a first input/output circuit configured to receive the rising data and the rising channel data; and
a second input/output circuit configured to receive the falling data and the falling channel data,
wherein the first input/output circuit generates a first edge signal and a first channel signal at a time point defined in the rising data, and the second input/output circuit generates a second edge signal and a second channel signal at a time point defined in the falling data.

4. The level shifter of claim 3 , further comprising:
a buffer control signal generation circuit connected to the first input/output circuit and the second input/output circuit, the buffer control signal generation circuit configured to output a buffer control signal,
wherein the buffer control signal is a first buffer control signal responsive to the buffer control signal generation circuit receiving the first edge signal from the first input/output circuit, and the buffer control signal is a second buffer control signal responsive to receiving the second edge signal from the second input/output circuit.

5. The level shifter of claim 4 , further comprising:
an output buffer configured to output a gate control signal according to the buffer control signal; and
a plurality of output circuits connected to the output buffer and the channel selection circuit.

6. The level shifter of claim 5 , wherein each of the plurality of output circuits includes a first switch connected to the output buffer, and the channel selection circuit is configured to turn on at least one of first switches of the plurality of output circuits according to the first channel signal or the second channel signal.

7. The level shifter of claim 6 , wherein each of the plurality of output circuits comprises:
a pull-up resistor having a first end connected to a gate-on voltage and a second end connected to a second switch; and
a pull-down resistor having a first end connected to a gate-off voltage and a second end connected to a third switch.

8. The level shifter of claim 7 , further comprising:
a switch control circuit connected between the buffer control signal generation circuit and the channel selection circuit, the switch control circuit configured to control the first switch, the second switch, and the third switch included in each of the plurality of output circuits according to the buffer control signal of the buffer control signal generation circuit,
wherein the channel selection circuit outputs control signals for the first switch to the third switch to the selected output circuit.

9. The level shifter of claim 8 , wherein the switch control circuit comprises:
a third logic circuit element configured to output a signal that controls the first switch according to the buffer control signal;
a fourth logic circuit element configured to output a signal that controls the second switch according to the buffer control signal;
a fifth logic circuit element configured to output a signal that controls the third switch according to the buffer control signal; and
a delay circuit configured to delay the buffer control signal to generate a delay signal, and output the delay signal to the third logic circuit element to the fifth logic circuit element.

10. The level shifter of claim 7 , comprising:
a second output maintaining circuit between the channel selection circuit and the second switch, the second output maintaining circuit connected to the second switch; and
a third output maintaining circuit between the channel selection circuit and the third switch, the third output maintaining circuit connected to the third switch;
wherein the second output maintaining circuit maintains a turn-on state of the second switch for a predetermined period of time while the second switch is turned on, and the third output maintaining circuit maintains a turn-on state of the third switch for a predetermined period of time while the third switch is turned on.

11. The level shifter of claim 10 , wherein each of the second output maintaining circuit and the third output maintaining circuit includes:
a first logic circuit element configured to invert a control signal and output a first signal based on the inverted control signal;
a second logic circuit element configured to receive the first signal from the first logic circuit, invert the first signal, and output a second signal; and
a feedback line connected to the second logic circuit element and the first logic circuit element, the feedback line configured to output the second signal output from the second logic circuit element to the first logic circuit element.

12. The level shifter of claim 1 , further comprising:
a plurality of first output maintaining circuits, each first output maintaining circuit connected a corresponding channel from the plurality of channels; and
a plurality of output circuits, each output circuit connected to a corresponding first output maintaining circuit from the plurality of first output maintaining circuits and to an output terminal from the plurality of output terminals that corresponds to the channel that is connected to the corresponding first output maintaining circuit,
wherein each of the plurality of first output maintaining circuits maintains a level of a gate control signal output from the output circuit that is connected to the first output maintaining circuit for a predetermined period of time.

13. The level shifter of claim 12 , wherein each of the plurality of first output maintaining circuits includes:
a first logic circuit element configured to receive a signal from the channel selection circuit, invert the signal, and output a first signal based on the inverted signal;
a second logic circuit element configured to receive the first signal from the first logic circuit element, invert the first signal, and output a second signal based on the inverted first signal; and
a feedback line connected to an output of the second logic circuit element and to an input of the first logic circuit element.

14. The level shifter of claim 13 , further comprising:
a first buffer connected to the second logic circuit element, the first buffer configured to convert the second signal f

Assignees

• Lg Display Co Ltd

Inventors

• Han Jae Won
• Cho Soon Dong
• Park Min Gyu
• Kim Sun Young
• Park Se Dong

Classifications

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2310/0289

  Details of voltage level shifters arranged for use in a driving circuit · CPC title

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title