Time synchronization of collecting and reporting power events between hierarchical power throttling circuits in a hierarchical power management system

Patent metadata

Field	Value
Publication number	US-12517565-B2
Application number	US-202418626683-A
Country	US
Kind code	B2
Filing date	Apr 4, 2024
Priority date	Jun 22, 2023
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The circuit levels in the hierarchical power management systems are configured to be time synchronized with each other for the synchronized monitoring and reporting of activity samples and activity power events, and the generation of power limiting management responses to throttle power consumption in the IC chip.

First claim

What is claimed is:

1 . A power management system in an integrated circuit (IC) chip configured to:
generate a local clock signal defining a plurality of local time windows each comprising a defined number of local pulses of the local clock signal; for each local time window of the plurality of local time windows:
synchronize an initial local pulse of the local time window based on a master clock signal;
sample processing activity of an assigned processing device of a plurality of processing devices within the local time window comprising the defined number of local pulses of the local clock signal to generate a plurality of activity samples;
determine a current flow rate of the assigned processing device within the local time window based on the plurality of activity samples;
estimate power consumption of the assigned processing device based on the plurality of activity samples within the local time window; and
generate an activity power event based on the estimated power consumption of the assigned processing device for the local time window; and
generate a second clock signal defining a plurality of second time windows each comprising a defined number of second pulses of the second clock signal; and for each second time window of the plurality of second time windows:
synchronize an initial second pulse in the second time window based on the master clock signal;
receive a plurality of activity power events generated by the power management system within the second time window; and
generate a power limiting management response to cause power consumption to be throttled in the IC chip based on the received plurality of activity power events for the second time window.

2 . The power management system of claim 1 , configured to generate the activity power event by being configured to generate the activity power event based on the estimated power consumption of the assigned processing device in response to a last pulse in the local time window.

3 . The power management system of claim 1 , further comprising for each assigned processing device a time synchronization circuit configured to generate a sync pulse to the master clock signal after every K first pulses of the master clock signal, wherein ‘K’ is a whole positive integer; and
further configured to:
synchronize the initial local pulse by being configured to synchronize the initial local pulse of the local clock signal in each local time window of the plurality of local time windows in response to the sync pulse.

4 . The power management system of claim 1 , wherein for each assigned processing device of the plurality of processing devices:
determine whether the current flow rate of the assigned processing device exceeds a threshold current flow rate; and in response to determining the current flow rate of the assigned processing device exceeds the threshold current flow rate:
throttle the processing activity of the assigned processing device to throttle its power consumption.

5 . The power management system of claim 1 , configured to for each local time window of the plurality of local time windows:
sample the processing activity of the assigned processing device comprising an assigned network node of the plurality of processing devices comprising a plurality of network nodes within the local time window comprising the defined number of local pulses of the local clock signal to generate the plurality of activity samples; and configured to:
determine the current flow rate by being configured to determine the current flow rate of the assigned network node within the local time window based on the plurality of activity samples;
estimate the power consumption by being configured to estimate the power consumption of the assigned network node based on the plurality of activity samples within the local time window; and
generate the activity power event by being configured to generate the activity power event based on the estimated power consumption of the assigned network node for the local time window.

6 . The power management system of claim 1 , further configured to determine whether a throughput in a processing device of the plurality of processing devices should be throttled based on the received plurality of activity power events within the second time window; and
in response to determining the throughput in the processing device of the plurality of processing devices should be throttled:
generate the power limiting management response by being configured to generate a throughput throttling power limiting management response to be received by the processing device to be throughput throttled for the second time window; and
configured to, for each assigned processing device of the plurality of processing devices:
receive the throughput throttling power limiting management response in response to generating the throughput throttling power limiting management response for its assigned processing device; and
throttle the processing activity of its assigned processing device to throttle its power consumption based on the received throughput throttling power limiting management response.

7 . The power management system of claim 1 , further configured to:
determine whether there are one or more missing activity power events from an expected number of the plurality of activity power events received within the second time window; and in response to determining the one or more missing activity power events, substitute the one or more missing activity power events in the plurality of activity power events with a corresponding one or more substitute activity power events.

8 . The power management system of claim 7 , configured to, in response to determining the one or more missing activity power events, substitute each of the one or more missing activity power events with a last received activity power event of the received plurality of activity power events in the second time window.

9 . The power management system of claim 7 , configured to, in response to determining the one or more missing activity power events, substitute each of the one or more missing activity power events with an average of a designated number of last received activity power events of the received plurality of activity power events in the second time window.

10 . The power management system of claim 7 , configured to, in response to determining the one or more missing activity power events, substitute each of the one or more missing activity power events with an activity power event programmed in a register.

11 . The power management system of claim 1 :
further configured to determine a throughput throttling for at least one processing device of the plurality of processing devices based on the received plurality of activity power events; and configured to, in response to determining the throughput throttling for the at least one processing device:
generate the power limiting management response by being configured to generate a throughput throttling power limiting management response to throttle throughput of the at least one processing device based on the received plurality of activity power events for the second time window.

12 . The power management system of claim 1 , configured to:
determine a clock throttling of at least one third clock circuit of one or more third clock circuits to clock at least one processing device of the plurality of processing devices, to clock throttle power consumption of at least one processing device of the plurality of processing devices based on the received plurality of activity power events; and in response to determining the clock throttling for the at l

Assignees

• Qualcomm Inc

Inventors

• Chamarty Vinod
• KOORAPATI Sagar
• Jayadev Sreeram
• Naveh Alon

Classifications

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title