Merging of power events related to estimated power consumption of different devices in a hierarchical power management system in an integrated circuit (IC) chip to perform power throttling

Patent metadata

Field	Value
Publication number	US-12228988-B2
Application number	US-202318339436-A
Country	US
Kind code	B2
Filing date	Jun 22, 2023
Priority date	Jun 22, 2023
Publication date	Feb 18, 2025
Grant date	Feb 18, 2025

Abstract

Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The hierarchical power management system includes a centralized power estimation and limiting (PEL) circuit that is configured to track and merge received power throttle recommendations associated with related activity power events for monitored processing devices to generate one or more power limiting management responses to throttle power consumption of related devices that may be contributing to excess power consumption.

First claim

What is claimed is:

1. An integrated circuit (IC) chip comprising a processor-based system, the processor-based system comprising:
a plurality of power rails each configured to carry power;
a plurality of processing devices each coupled to at least one power rail of the plurality of power rails; and
a hierarchical power management system, comprising:
a plurality of local area management (LAM) circuits each configured to:
sample processing activity of an assigned processing device of the plurality of processing devices into a plurality of activity samples;
estimate power consumption of the assigned processing device based on the plurality of activity samples of the assigned processing device; and
generate an activity power event based on the estimated power consumption of the assigned processing device; and

a power estimation and limiting (PEL) circuit configured to:
receive the plurality of activity power events generated by the plurality of LAM circuits;
determine a plurality of activity power throttle recommendations each corresponding to a respective assigned processing device of the plurality of processing devices, based on the received plurality of activity power events and a plurality of activity power limiting management policies;
merge the received plurality of activity power throttle recommendations into one or more merged power throttle recommendations;
determine a power limiting management response to throttle power consumption in one or more target devices in the IC chip based on the one or more merged power throttle recommendations, wherein the one or more target devices includes at least one target device not associated with the plurality of activity power events used to determine the plurality of activity power throttle recommendations; and
generate the power limiting management response to cause the power consumption to be throttled in the one or more target devices in the IC chip.

2. The IC chip of claim 1 , wherein the power limiting management response is based on a merged power throttle recommendation of the one or more merged power throttle recommendations that is not associated with the plurality of processing devices.

3. The IC chip of claim 1 , wherein the power limiting management response is based on a merged power throttle recommendations of the one or more merged power throttle recommendations that is associated with a processing device of the plurality of processing devices.

4. The IC chip of claim 1 , wherein:
the one or more merged power throttle recommendations comprises a plurality of merged power throttle recommendations; and
the PEL circuit is further configured to:
determine a second power limiting management response to throttle power consumption in a second one or more target devices of the plurality of processing devices in the IC chip based on the plurality of merged power throttle recommendations; and
generate the second power limiting management response to cause power consumption to be throttled in the second one or more target devices in the IC chip.

5. The IC chip of claim 1 , wherein:
the PEL circuit is further configured to:
receive a plurality of energy power events;

the PEL circuit is further configured to:
determine a plurality of energy power throttle recommendations based on the received plurality of energy power events and a plurality of energy power limiting management policies each corresponding to a target device in the IC chip;

the PEL circuit configured to:
merge the received plurality of power throttle recommendations by being configured to merge the plurality of activity power throttle recommendations and the plurality of energy power throttle recommendations into the one or more merged power throttle recommendations.

6. The IC chip of claim 1 , wherein the plurality of activity power limiting management policies each comprise one or more threshold power consumptions;
the PEL circuit configured to determine the plurality of activity power throttle recommendations, by being configured to compare a power consumption indicated by each of the received plurality of activity power events to the one or more threshold power consumptions of the respective plurality of activity power limiting management policies.

7. The IC chip of claim 1 , wherein the plurality of activity power limiting management policies each comprise a plurality of different threshold power consumptions;
the PEL circuit configured to determine the plurality of activity power throttle recommendations, by being configured to compare a power consumption indicated by each of the received plurality of activity power events to each of the plurality of threshold power consumptions of the respective plurality of activity power limiting management policies.

8. The IC chip of claim 1 , wherein:
the PEL circuit is further configured to:
perform a weighting of the plurality of activity power events based on a respective plurality of weight values to generate a plurality of weighted activity power events;
determine the plurality of activity power throttle recommendations by being configured to determine the plurality of activity power throttle recommendations each corresponding to a respective activity power event of the plurality of activity power events, based on the plurality of weighted activity power events and a plurality of activity power limiting management policies.

9. The IC chip of claim 8 , wherein the PEL circuit is further configured to increase the weighting of one or more weighted activity power events of the plurality of weighted activity power events based on the respective plurality of weight values.

10. The IC chip of claim 8 , wherein the PEL circuit is further configured to decrease the weighting of one or more weighted activity power events of the plurality of weighted activity power events based on the respective plurality of weight values.

11. The IC chip of claim 1 , wherein the PEL circuit further comprises:
a plurality of tracker circuits;
each tracker circuit of the plurality of tracker circuits configured to:
receive the plurality of activity power events;
aggregate the plurality of activity power events into an aggregated activity power event;
compare a power consumption indicated by the aggregated activity power event to an activity power limiting management policy of the plurality of activity power limiting management policies assigned to the tracker circuit; and
generate an activity power throttle recommendation of the plurality of activity power throttle recommendations based on the comparison of the power consumption indicated by the aggregated activity power event to the activity power limiting management policy.

12. The IC chip of claim 11 , wherein PEL circuit is further configured to decode the received plurality of activity power events to a designated tracker circuit of the plurality of tracker circuits into a plurality of decoded activity power events.

13. The IC chip of claim 11 , wherein:
each tracker circuit of the plurality of tracker circuits is further configured to:
reset the aggregated activity power event in each time window of a plurality of consecutive time windows; and

each tracker circuit of the plurality of tracker circuits is configured to:
compare the power consumption indicated by the aggregated activity power event to an activity power limiting management policy of the plurality of activity power limiting management policies assigned to the tracker circuit in each time window of the plurality of consecutive time windows.

14. The IC chip of claim 11 , wherein each tracker circuit of the plurality of tracker

Assignees

• Qualcomm Inc

Inventors

• KOORAPATI Sagar
• Naveh Alon

Classifications

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F1/32

  Means for saving power · CPC title

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title