Hazard mitigation for lightweight processor cores

Patent metadata

Field	Value
Publication number	US-12511122-B2
Application number	US-202016875804-A
Country	US
Kind code	B2
Filing date	May 15, 2020
Priority date	May 15, 2020
Publication date	Dec 30, 2025
Grant date	Dec 30, 2025

Abstract

Integrated circuits that include lightweight processor cores are provided. Each processor core may be configured to execute a series of instructions. At least one of the instructions may include an embedded delay field with a value specifying the amount of time that instruction needs to wait before proceeding to the next instruction to avoid a data hazard. The value of the delay field may be determined by a compiler during software compile time. Such delay field may also be used in conjunction with branch instructions to specify a number of no-operations (NOPs) for one or more associated branch delay slots and may also be used to reduce data forwarding cost.

First claim

What is claimed is:

1 . An integrated circuit, comprising:
program memory; and a processor core of a programmable logic device configured to execute a plurality of instructions stored on the program memory, the processor core having a pipeline with one or more pipeline levels, at least a first pipeline level having first forwarding logic based on a first determined forward frequency that the first forwarding logic is to be used by the processor core and at least a second pipeline level not having second forwarding logic based on a second determined forward frequency that the second forwarding logic is to be used by the processor core, wherein at least one instruction in the plurality of instructions comprises a NOP that comprises a delay field having a value encoded that indicates how often the NOP is to be inserted to avoid a data hazard, and the value is based at least in part on a frequency used in the programmable logic device.

2 . The integrated circuit of claim 1 , wherein the value of the delay field specifies that multiple NOPs are inserted into the pipeline of the processor core after the at least one instruction to avoid the data hazard.

3 . The integrated circuit of claim 1 , wherein a first additional instruction in the plurality of instructions does not have a delay field for preventing a data hazard for the first additional instruction.

4 . The integrated circuit of claim 3 , wherein a second additional instruction following the first additional instruction in the plurality of instructions specifies multiple NOPs to prevent the data hazard for the first additional instruction.

5 . The integrated circuit of claim 1 , wherein the at least one instruction comprises a branch instruction with an associated branch delay slot, and wherein the delay field specifies whether the branch delay slot is filled by the NOP or another instruction in the plurality of instructions.

6 . The integrated circuit of claim 1 , wherein the at least one instruction comprises a branch instruction with multiple associated branch delay slots, and wherein the delay field specifies whether one or more of the multiple branch delay slots are filled by NOPs or other instructions in the plurality of instructions.

7 . The integrated circuit of claim 1 , wherein the processor core is at least partially implemented using programmable logic, and wherein the value of the delay field is dynamically adjustable.

8 . The integrated circuit of claim 1 , wherein at least some of the plurality of instructions uses the first forwarding logic.

9 . The integrated circuit of claim 8 , wherein the first forwarding logic comprises forwarding multiplexers configured to receive signals from the first pipeline level, wherein the first pipeline level comprises a deeper pipeline stage in the processor core.

10 . The integrated circuit of claim 1 , further comprising:
a counter circuit configured to count a number of inserted NOPs specified by the delay field to avoid the data hazard.

11 . The integrated circuit of claim 1 , wherein the programmable logic device comprises a field programmable gate array (FPGA).

12 . A method of implementing a processor, comprising:
using a compiler to compile a source code for a programmable logic device prior to run time by assigning registers to operations in the source code and to generate a corresponding machine code with a plurality of instruction words; analyzing, by the compiler prior to run time, the registers to detect a data hazard associated with the operations; determining, by the compiler, an amount of delay that is required to remove the data hazard; determining, by the compiler, a forwarding frequency that forwarding circuitry of each level of a pipeline executed by the processor is to be used; removing, by the compiler, the forwarding circuitry for one or more levels of the pipeline based on the forwarding frequency that the forwarding circuitry of the one or more levels is to be used; encoding, by the compiler prior to run time, the amount of delay in a delay field in a NOP of a given instruction word in the plurality of instruction words to indicate how often to insert the NOP, wherein the amount of delay is based at least in part on a frequency used in the programmable logic device; and using the processor to execute the plurality of instruction words in the machine code.

13 . The method of claim 12 , wherein the delay field is statically set by the compiler.

14 . The method of claim 12 , wherein the delay field is dynamically adjustable.

15 . The method of claim 12 , wherein the delay field specifies that one or more NOPs has to be inserted after the given instruction word when using the processor to execute the machine code.

16 . The method of claim 12 , wherein the given instruction word has an opcode portion and an operand portion, and wherein the delay field is within an unused part of the opcode portion or the operand operation.

17 . The method of claim 12 , further comprising:
determining whether a first additional instruction word in the plurality of instruction words results in a potential data hazard; and in response to determining that the first additional instruction word results in a potential data hazard, using a second additional instruction word in the plurality of instruction words following the first additional instruction word to specify multiple NOP iterations to prevent the potential data hazard for the first additional instruction word.

18 . A method of implementing a processor, comprising:
using a compiler to compile a source code for a programmable logic device prior to run time by assigning registers to operations in the source code and to generate a corresponding machine code having a first instruction immediately followed by a second instruction, wherein the second instruction is issued a number of clock cycles after the first instruction as indicated by a value of a delay field of a NOP indicating how often the NOP is to be inserted between the first and second instruction, and the value is based at least in part on a frequency used in the programmable logic device; determining, by the compiler, a forwarding frequency that forwarding circuitry of each level of a pipeline executed by a processor core is to be used; removing, by the compiler, the forwarding circuitry for one or more levels of the pipeline based on the forwarding frequency that the forwarding circuitry of the one or more levels is to be used; analyzing, by the compiler prior to runtime, the registers to detect a situation where a value required for the second instruction is already available due to execution of the first instruction; and in response to detecting that the value required for the second instruction is already available due to the execution of the first instruction, opportunistically reducing an execution time of the second instruction.

19 . The method of claim 18 , wherein the number of clock cycles is predetermined as equal to or greater than two clock cycles.

20 . The method of claim 18 , wherein the value of the delay field specifies that multiple NOPs are inserted into the pipeline of the processor core.

21 . The method of claim 18 , wherein a third instruction in the machine code does not have a delay field for preventing data hazard for the third instruction.

Assignees

• Intel Corp
• Altera Corp

Inventors

• Langhammer Martin
• Baeckler Gregg William

Classifications

• G06F9/30058

  Conditional branch instructions · CPC title

• G06F8/44

  Encoding · CPC title

• G06F9/30098

  Register arrangements · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/30185

  according to one or more bits in the instruction, e.g. prefix, sub-opcode · CPC title