Display panel and display device

Patent metadata

Field	Value
Publication number	US-12507476-B2
Application number	US-202117534459-A
Country	US
Kind code	B2
Filing date	Nov 24, 2021
Priority date	Dec 30, 2020
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

Provided are a display panel and a display device. The display panel includes a base substrate, a first transistor, and a second transistor. The first transistor and the second transistor are formed on the base substrate, the first transistor includes a first active layer, a first gate, a first source, and a first drain, and the first active layer comprises silicon; the second transistor includes a second active layer, a second gate, a second source, and a second drain, and the second active layer comprises an oxide semiconductor and is disposed on one side of the first active layer facing away from the base substrate. In a first direction perpendicular to the base substrate, a first distance between the first gate and the first active layer is D 1 , a second distance between the second gate and the second active layer is D 2 , and D 1 <D 2.

First claim

What is claimed is:

1 . A display panel, comprising:
a base substrate; and a first transistor and a second transistor, wherein the first transistor and the second transistor are formed on the base substrate, the first transistor comprises a first active layer, a first gate, a first source, and a first drain, and the first active layer comprises silicon; the second transistor comprises a second active layer, a second gate, a second source, and a second drain, and the second active layer comprises an oxide semiconductor and is disposed farther away from the base substrate than the first active layer; wherein the first gate is disposed on top of the first active layer, and the second gate is disposed on top of the second active layer; wherein, in a first direction perpendicular to the base substrate, a first distance between the first gate and the first active layer is D 1 , a second distance between the second gate and the second active layer is D 2 , and D 1 <D 2 ; wherein the display panel further comprises a pixel circuit and a drive circuit providing a drive signal for the pixel circuit, wherein the drive circuit comprises the second transistor, and either the pixel circuit comprises the first transistor or the drive circuit comprises the first transistor; wherein the pixel circuit comprises a third transistor, the third transistor comprises a third active layer, a third gate, a third source, and a third drain, and the third active layer comprises an oxide semiconductor; and in the direction perpendicular to the base substrate, a third distance between the third gate and the third active layer is D 3 , and D 1 <D 3 ; wherein the second gate is located on one side of the first active layer facing away from the base substrate, and the third gate is disposed on one side of the third active layer facing away from the base substrate; the second transistor comprises a fourth gate, the third transistor comprises a fifth gate, the fourth gate is disposed on one side of the second active layer facing towards the base substrate, and the fifth gate is disposed on one side of the third active layer facing towards the base substrate; and in the first direction perpendicular to the base substrate, a fourth distance between the fourth gate and the second active layer is D 4 , a fifth distance between the fifth gate and the third active layer is D 5 , D 1 <D 4 , and D 1 <D 5 ; wherein D 2 <D 4 and D 3 <D 5 , the third transistor is a drive transistor of the pixel circuit, a second length of the second gate in a second direction is L 2 , a third length of the third gate in the second direction is L 3 , a fourth length of the fourth gate in the second direction is L 4 , and a fifth length of the fifth gate in the second direction is L 5 ;
( L 3− L 2)<( L 5− L 4); and

the second direction is a direction pointing from the first source to the first drain.

2 . The display panel of claim 1 , wherein
the drive circuit comprises an input module, a logic transmission module, and an output module, the input module is connected between an input terminal and the logic transmission module, and the output module is connected between the logic transmission module and an output terminal; the logic transmission module is connected to a logic high-level signal terminal or a logic low-level signal terminal, and the output terminal is connected to the pixel circuit; and the output module comprises the first transistor and either the logic transmission module comprises the second transistor or the input module comprises the second transistor.

3 . The display panel of claim 2 , wherein
a first width of a first channel region of the first transistor is W 1 , a second width of a second channel region of the second transistor is W 2 , a first length of the first channel region of the first transistor is L 1 , and a second length of the second channel region of the second transistor is L 2 ; and a first width-to-length ratio of the first transistor is R 1 =W 1 /L 1 , a second width-to-length ratio of the second transistor is R 2 =W 2 /L 2 , and R 1 /R 2 ≥D 1 /D 2 .

4 . The display panel of claim 1 , wherein
a first width of a first channel region of the first transistor is W 1 , a second width of a second channel region of the second transistor is W 2 , a first length of the first channel region of the first transistor is L 1 , a second length of the second channel region of the second transistor is L 2 , and W 1 /L 1 ≤W 2 /L 2 .

5 . The display panel of claim 4 , wherein
a first width-to-length ratio of the first transistor is R 1 =W 1 /L 1 , a second width-to-length ratio of the second transistor is R 2 =W 2 /L 2 , and R 1 /R 2 ≤D 1 /D 2 ; the drive circuit comprises an input module, a logic transmission module, and an output module, the input module is connected between an input terminal and the logic transmission module, and the output module is connected between the logic transmission module and an output terminal; the output terminal is connected to the pixel circuit, and either the logic transmission module is connected to a logic high-level signal terminal or a logic low-level signal terminal; and the output module comprises the second transistor.

6 . The display panel of claim 1 , wherein
the third transistor is a switch transistor of the pixel circuit, and D 2 ≤D 3 .

7 . The display panel of claim 1 , wherein
the third transistor is a drive transistor of the pixel circuit, and D 2 <D 3 .

8 . The display panel of claim 1 , wherein
the third transistor is a drive transistor of the pixel circuit, and
( D 4− D 2)>( D 5− D 3).

9 . The display panel of claim 8 , wherein
D 3 >D 2 and D 5 <D 4 .

10 . The display panel of claim 1 , further comprising: a first insulating layer, a second insulating layer and a third insulating layer, wherein
the first insulating layer is disposed between the first gate and the first active layer, the second insulating layer is disposed between the second gate and the second active layer, and a third insulating layer is disposed between the third gate and the third active layer; and a first concentration of hydrogen in the third insulating layer is higher than a second concentration of hydrogen in the second insulating layer.

11 . The display panel of claim 1 , wherein
the pixel circuit further comprises a fourth transistor, the fourth transistor comprises a fourth active layer, a sixth gate, a fourth source, and a fourth drain, and the fourth active layer comprises an oxide semiconductor; and in the first direction perpendicular to the base substrate, a sixth distance between the sixth gate and the fourth active layer is D 6 , and D 1 <D 6 .

12 . The display panel of claim 11 , wherein
the third transistor is a drive transistor of the pixel circuit, the fourth transistor is a switch transistor of the pixel circuit, and D 3 >D 6 .

13 . The display panel of claim 12 , wherein
the third transistor comprises a fifth gate, the third gate and the fifth gate are located on two sides of the third active layer, respectively; the fourth transistor comprises a seventh gate, and the sixth gate and the seventh gate are located on two sides of the fourth active layer, respectively; and in the first direction perpendicular to the base substrate, a fifth distance between the fifth gate and the third active layer is D 5 , a seventh distance between the seventh gate and the fourth active layer is D 7 , and (D 5 −D 3 )<(D 7 −D 6 ).

14 . The display panel of claim 13 , wherein
a third length of the third gate in a second direction is L 3 , a fifth length of the fifth gat

Assignees

• Xiamen Tianma Micro Electronics Co Ltd

Inventors

• He Shui
• An Ping

Classifications

• H10D86/423 Primary

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10D86/431

  having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs · CPC title