Gate aligned fin cut for advanced integrated circuit structure fabrication

Patent metadata

Field	Value
Publication number	US-12507464-B2
Application number	US-202117339160-A
Country	US
Kind code	B2
Filing date	Jun 4, 2021
Priority date	Jun 4, 2021
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

Gate aligned fin cut for advanced integrated circuit structure fabrication is described. For example, an integrated circuit structure includes a first fin segment having a fin end, and a second fin segment spaced apart from the first fin segment, the second fin segment having a fin end facing the fin end of the first fin segment. A first gate structure is over the first fin segment, the first gate structure substantially vertically aligned with the fin end of the first fin segment. A second gate structure is over the second fin segment, the second gate structure substantially vertically aligned with the fin end of the second fin segment. An isolation structure is laterally between the fin end of the first fin segment and the fin end of the second fin segment.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a first fin segment having a fin end; a second fin segment spaced apart from the first fin segment, the second fin segment having a fin end facing the fin end of the first fin segment; a first gate structure over the first fin segment, the first gate structure substantially vertically aligned with the fin end of the first fin segment; a second gate structure over the second fin segment, the second gate structure substantially vertically aligned with the fin end of the second fin segment; and an isolation structure laterally between the fin end of the first fin segment and the fin end of the second fin segment, the isolation structure having a bottommost surface below a bottommost surface of the first fin segment and a bottommost surface of the second fin segment.

2 . The integrated circuit structure of claim 1 , wherein the second fin segment is a dummy fin segment.

3 . The integrated circuit structure of claim 1 , wherein the first fin segment comprises an epitaxial source or drain structure at a second fin end of the first fin segment, and the second fin segment does not comprise an epitaxial source or drain structure at a second fin end of the second fin segment.

4 . The integrated circuit structure of claim 1 , wherein the fin comprises a plurality of horizontally stacked nanowires.

5 . The integrated circuit structure of claim 1 , wherein the fin is a unitary body.

6 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, the integrated circuit structure comprising:
a first fin segment having a fin end;
a second fin segment spaced apart from the first fin segment, the second fin segment having a fin end facing the fin end of the first fin segment;
a first gate structure over the first fin segment, the first gate structure substantially vertically aligned with the fin end of the first fin segment;
a second gate structure over the second fin segment, the second gate structure substantially vertically aligned with the fin end of the second fin segment; and
an isolation structure laterally between the fin end of the first fin segment and the fin end of the second fin segment, the isolation structure having a bottommost surface below a bottommost surface of the first fin segment and a bottommost surface of the second fin segment.

7 . The computing device of claim 6 , further comprising:
a memory coupled to the board.

8 . The computing device of claim 6 , further comprising:
a communication chip coupled to the board.

9 . The computing device of claim 6 , wherein the component is a packaged integrated circuit die.

10 . The computing device of claim 6 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Assignees

• Intel Corp

Inventors

• Guler Leonard P
• Hasan Mohammad
• Hsu William
• Guha Biswajeet
• Wallace Charles H
• Ghani Tahir
• Pursel Sean
• Chang Tsuan-Chung

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10D84/0151 Primary

  Manufacturing their isolation regions · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D84/013

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title