Semiconductor device

Patent metadata

Field	Value
Publication number	US-12507446-B2
Application number	US-202318346480-A
Country	US
Kind code	B2
Filing date	Jul 3, 2023
Priority date	Nov 30, 2016
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

A method includes forming a fin in a substrate. The fin is etched to create a source/drain recess. A source/drain feature is formed in the source/drain recess, in which a lattice constant of the source/drain feature is greater than a lattice constant of the fin. An epitaxy coat is grown over the source/drain feature, in which a lattice constant of the epitaxy coat is smaller than a lattice constant of the fin.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a semiconductor substrate; a silicon fin structure protruding over the semiconductor substrate; an isolation structure alongside a bottom portion of the silicon fin structure; a gate stack crossing the silicon fin structure; and a source/drain region over the silicon fin structure, wherein the source/drain region comprising a silicon germanium epitaxy structure and a silicon phosphorus epitaxy coat over the silicon germanium epitaxy structure, wherein the silicon phosphorus epitaxy coat crosses the silicon germanium epitaxy structure and in contact with a top surface of the isolation structure.

2 . The semiconductor device of claim 1 , wherein a lattice constant of the silicon phosphorus epitaxy coat is smaller than a lattice constant of the silicon fin structure.

3 . The semiconductor device of claim 2 , wherein a lattice constant of the silicon germanium epitaxy structure is greater than the lattice constant of the silicon fin structure.

4 . The semiconductor device of claim 1 , wherein the silicon phosphorus epitaxy coat extends along a top surface and sidewalls of an upper portion of the silicon germanium epitaxy structure.

5 . The semiconductor device of claim 1 , wherein the silicon germanium epitaxy structure has a bar-like cross-section.

6 . A semiconductor device comprising:
a semiconductor substrate; an N-type transistor over the semiconductor substrate, comprising:
a first fin structure;
an isolation structure alongside a bottom portion of the first fin structure; a first gate stack over the first fin structure; and
a first source/drain region over the first fin structure, wherein the first source/drain region comprises a first epitaxy structure and an epitaxy coat over the first epitaxy structure, and a lattice constant of the epitaxy coat is smaller than a lattice constant of the first fin structure, wherein the epitaxy coat crosses the first epitaxy structure and is in contact with a top surface of the isolation structure, and wherein the epitaxy coat is made of silicon phosphorus and the first epitaxy structure is made of silicon germanium; and
a P-type transistor over the semiconductor substrate, comprising:
a second fin structure;
a second gate stack over the second fin structure; and
a second source/drain region over the second fin structure, wherein the second source/drain region comprises a second epitaxy structure, and wherein a surface of the second epitaxy structure is free of coverage by a material of the epitaxy coat of the first source/drain region.

7 . The semiconductor device of claim 6 , wherein the first epitaxy structure and the second epitaxy structure both include a bar-like cross-section.

8 . The semiconductor device of claim 6 , wherein a lattice constant of the first epitaxy structure is greater than the lattice constant of the first fin structure, and a lattice constant of the second epitaxy structure is greater than a lattice constant of the second fin structure.

9 . The semiconductor device of claim 6 , wherein the epitaxy coat extends along a top surface and sidewalls of an upper portion of the first epitaxy structure.

10 . The semiconductor device of claim 6 , wherein a top portion of the first fin structure protrudes from the top surface of the isolation structure.

11 . The semiconductor device of claim 6 , wherein the first fin structure is made of silicon.

12 . The semiconductor device of claim 6 , wherein the second epitaxy structure comprise silicon germanium.

13 . A semiconductor device comprising:
a semiconductor substrate; a fin structure protruding over the semiconductor substrate; an isolation structure alongside a bottom portion of the fin structure; a gate stack crossing the fin structure; gate spacers on opposite sidewalls of the gate stack; and a source/drain region over the fin structure, wherein the source/drain region comprising an epitaxy structure and an epitaxy coat lining sidewalls and a top surface of the epitaxy structure, wherein the epitaxy coat is in contact with a top surface of the isolation structure, and wherein the epitaxy coat is made of silicon phosphorus and the epitaxy structure is made of silicon germanium.

14 . The semiconductor device of claim 13 , wherein the fin structure is made of silicon.

15 . The semiconductor device of claim 13 , wherein a lattice constant of the epitaxy coat is smaller than a lattice constant of the fin structure.

16 . The semiconductor device of claim 13 , wherein a top portion of the fin structure protrudes from the top surface of the isolation structure.

17 . The semiconductor device of claim 13 , wherein the epitaxy structure has a bar-like cross-section.

18 . The semiconductor device of claim 13 , wherein the epitaxy coat is separated from the fin structure through the epitaxy structure.

19 . The semiconductor device of claim 13 , wherein a dopant concentration of the epitaxy coat gradually decreases from a first portion of the epitaxy coat to a second portion of the epitaxy coat below the first portion of the epitaxy coat.

20 . The semiconductor device of claim 13 , wherein the epitaxy coat has a dopant concentration between about 3×10 21 /cm 3 and 4×10 21 /cm 3 .

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Wei-Yang
• Chen Ting-Yeh
• Li Chii-Horng
• Yang Feng-Cheng

Classifications

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D84/853

  comprising FinFETs · CPC title